Principal Signal Integrity Engineer

Hewlett Packard Enterprise Company; Sunnyvale (CA); Vor Ort; USD 181.000 - 367.000; Vollzeit

Zusammenfassung

Hewlett Packard Enterprise seeks a Principal Signal Integrity Engineer to join an experienced SI team in Sunnyvale, CA. You will analyze high-speed ASIC PAM4 SerDes and system-level SI for cutting-edge networking products, driving design trade-offs across ASIC, board, and connectors.

You will work with CAD tools (HFSS, SIwave, ADS, Allegro, Sigrity, MATLAB) and lab equipment to ensure robust signal and power integrity across channels up to 200G.

Qualifikationen

• Typically 10+ years of SI analysis with a relevant engineering degree.
• Typically 8+ years with a master's degree in related fields.
• Experience with 56G/112G ASIC PAM4 SerDes required.
• Hands-on experience with up to 200G serial channels and TP1A measurements.

Aufgaben

• Perform channel margin analysis to trade off ASIC package, board and connectors.
• Develop PAM4 SerDes channel models and correlate with test structures.
• Correlate simulations with measurements and improve model accuracy.
• Perform PCB timing analysis and document SI design rules.
• TTuning SerDes parameters to improve design margins and perform DVT measurements.

Kenntnisse

Signal Integrity

High-speed design

Team collaboration

Ausbildung

Bachelor's degree in Electrical Engineering or related

Master's degree in Electrical Engineering or related

Tools

Ansys HFSS

SIwave

ADS

Allegro

Sigrity

MATLAB

Jobbeschreibung

Principal Signal Integrity Engineer

This role has been designed as ''Onsite' with an expectation that you will primarily work from an HPE office.

Who We Are:

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world. Our culture thrives on finding new and better ways to accelerate what's next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.

Job Description:

Work with an experienced signal integrity team with many years of experience performing high speed ASIC PAM4 SerDes and system-level signal and power Integrity analysis for cutting edge networking product design.

Team members are industry experts with hands-on experience with high-speed ASIC PAM4 SerDes, channel analysis, clocking, I/O timing, on-die power integrity, system-level power integrity, CPM model and PDN optimization, PCB design for SI and PI.

Key Responsibilities:

• Perform COM (channel margin analysis) to provide design trade-offs amongst ASIC package, board, and connectors. Develop ASIC PAM4 SerDes channel simulation models and correlate to test structures.
• Correlate ASIC PAM4 SerDes simulation results with Measurements and work with component and ASIC vendors to improve model accuracy.
• Perform PCB timing analysis, work with board engineers and layout designers to implement all design SI rules, develop and document all layout/SI design rules and checklists.
• ASIC PAM4 SerDes parametric tuning to improve design margins of serial links.
• Perform SI DVT measurements on boards and correlate simulations with DVT measurements. Provide technical assessment of projects to SI management team.

Basic Requirements:

• Typically, 10 + years of Signal Integrity analysis experience with a bachelor's degree in Electrical engineering, Computer engineering, Microwave, and/or RF engineering.
• Typically, 8 + years of Signal Integrity analysis experience with a master's degree in Electrical engineering, Computer engineering, Microwave, and/or RF engineering.
• Experience with 56G/112G ASIC PAM4 SerDes technologies is required.
• 200G ASIC PAM4 experience desired.
• Hands-on experience in serial channels up to 200G line rates for coefficient tuning, TP1A measurements.

Preferred Skills:

• Proficient with CAD tools such as Ansys HFSS, SIwave ADS, Allegro, Sigrity and MATLAB.
• Proficient with lab equipment such as oscilloscopes, Vector Network Analyzers, Time Domain Reflectometers, Spectrum Analyzers, phase noise Analyzers. Good lab debug skills a plus.
• Strong capabilities to debug and provide solutions for ASIC PAM4 SerDes and channel performance issues.
• Design implementation for system clocks and solid understanding of PLL design and debug.
• PCB Stack-up design using 2-d field solvers.

Knowledge and Skills:

• Good oral and written communication skills.
• Team player able to collaborate with people across geography and in a matrix organization.
• Capable of working on several projects simultaneously.

Accessibility

HPE is committed to creating an inclusive and accessible workplace and encourages applications from all qualified individuals, including those with disabilities. If you believe you require accommodation during any stage of the application or interview process, please submit your request by completing our secure form linked here .

Note: This option is reserved for applicants needing assistance/reasonable accommodation related to a disability.

What We Can Offer You:

Health & Wellbeing

We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.

Personal & Professional Development

We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have - whether you want to become a knowledge expert in your field or apply your skills to another division.

Unconditional Inclusion

We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.

Let's Stay Connected:

Follow @HPECareers on Instagram to see the latest on people, culture and tech at HPE.

#unitedstates

#networking

Job:

Engineering

Job Level:

TCP_05

"The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.
- United States of America: Annual Salary USD 181,000 - 367,000 in California
The listed salary range reflects base salary. Variable incentives may also be offered."

Information about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html

HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together.

Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.

HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.