Senior SI Engineer – PAM4/SerDes (Onsite)

Hewlett Packard Enterprise; Sunnyvale (CA); On-site; USD 181,000 - 367,000; Full time

Job summary

Hewlett Packard Enterprise is seeking a Principal Signal Integrity Engineer to join an onsite team in California. You will work on high-speed ASIC PAM4 SerDes and system‑level signal and power integrity analyses for advanced networking products.

Responsibilities include channel margin analysis, model development, and coordinating with ASIC vendors to improve accuracy. You will also perform PCB timing analysis, SI rule documentation, and SerDes parameter tuning to boost design margins.

Qualifications

• 10+ years of Signal Integrity analysis experience with a relevant engineering degree.
• 8+ years of SI experience with a Master’s degree in EE/CE/Microwave/RF.
• Experience with 56G/112G ASIC PAM4 SerDes technologies is required.
• 200G PAM4 experience desired.

Responsibilities

• Perform COM (channel margin) analysis to trade off ASIC package, board, and connectors; develop PAM4 SerDes channel models and correlate to test structures.
• Correlate PAM4 SerDes simulation results with measurements and improve models with vendors.
• Perform PCB timing analysis and enforce all SI rules with board engineers and layout designers.
• ASIC PAM4 SerDes parametric tuning to improve design margins.
• Perform SIDVT measurements on boards and correlate simulations with DVT measurements.

Skills

Signal Integrity

SerDes

Channel analysis

PCB timing

Education

Bachelor's in Electrical/Computer/Microwave/RF

Master's in Electrical/Computer/Microwave/RF

Tools

Ansys HFSS

SIwave

Allegro

Sigrity

MATLAB

Job description

Hewlett Packard Enterprise is seeking a Principal Signal Integrity Engineer to join an onsite team in California. You will work on high-speed ASIC PAM4 SerDes and system‑level signal and power integrity analyses for advanced networking products.

Responsibilities include channel margin analysis, model development, and coordinating with ASIC vendors to improve accuracy. You will also perform PCB timing analysis, SI rule documentation, and SerDes parameter tuning to boost design margins.