Lead SerDes Design & Validation Engineer

Apple

Cupertino (CA)

On-site

USD 180,000 - 230,000

Full time

5 days ago

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Job summary

Apple is seeking a SerDes Design and Validation Engineer to lead system validation of high-speed SerDes IP in a cutting-edge SOC environment. You will own the bring-up, validation and debug of analog/mixed-signal blocks, and drive test plans and data analysis with production-test teams.

The role requires hands-on experience with lab testing and knowledge of PCIe/USB/DP/MPHY protocols, aiming to deliver robust silicon and competitive performance while collaborating across design and validation

Qualifications

BS and a minimum of 10 years relevant industry experience.
Experience in high-speed serial links and analog mixed-signal circuit blocks including Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, Filters.
Experience with digitally assisted analog design concepts (e.g. background calibrations, LMS based adaptive loops).
Hands-on experience with lab and production testing, debug, and data analysis.
Familiarity with common high-speed SerDes protocols such as PCIe, USB, DP, and MPHY; knowledge of TX/RX equalization (CTLE/DFE/de-emphasis) and CDR architectures.

Responsibilities

Own SerDes system bring-up, validation and debug.
Define DFT needs to help enhance testability and first-time silicon success.
Involve in mixed-signal verification to understand SerDes operation and interactions with higher level control logic.