Senior SerDes Clocking Architect: Ultra-Low-Jitter PLLs

Upscale AI; California; On-site; USD 220,000 - 350,000; Full time

Job summary

Upscale, Inc. is building world-class SerDes clocking for AI data centers. We seek a senior technical leader to define clocking architecture, PLLs, and distribution for 5nm CMOS, collaborating across analog, mixed-signal, digital, layout, and silicon validation teams.

You will drive architectural innovation, lead critical clocking development, and tackle jitter, coupling, and power-efficiency challenges. This role combines hands-on design with system-level verification and cross-functional

Qualifications

• MS or PhD in Electrical Engineering or related field.
• Experience delivering ultra-low-jitter PLLs (100 fs-class RMS) in 5nm CMOS.
• Deep expertise in PLL architecture, including phase detectors, charge pumps, loop filters, and oscillators.
• Strong understanding of phase noise, jitter, reference spurs, loop stability and clock quality on SerDes.
• Proven ability to define clocking architectures from system requirements to circuit specs.
• Experience with clock distribution design, skew, power integrity, and electromagnetic interactions.
• Hands-on experience with electromagnetic simulation and extraction tools.
• Experience developing SystemVerilog-based behavioral models and verification environments for PLLs.
• Strong technical leadership and silicon-delivery track record.

Responsibilities

• Define end-to-end clocking architecture for next-gen SerDes including PLLs, clock generation, and distribution.
• Lead ultra-low-jitter PLL design targeting sub-100 fs RMS jitter in 5nm CMOS.
• Evaluate and trade off hybrid and digital PLL architectures for jitter, power, area, and robustness.
• Develop solutions to mitigate coupling among multiple PLLs and clock blocks.
• Implement advanced clock distribution with resonant techniques to reduce power and maintain timing.
• Use electromagnetic tools to analyze inductors, resonant networks, and interconnects.
• Develop SystemVerilog models and verification environments for PLLs and clock subsystems.
• Collaborate with SerDes TX/RX, ADC, AMS layout, and silicon-validation teams.
• Drive design reviews, silicon characterization, jitter analysis, and silicon correlation.

Skills

Clocking architecture

PLL design

High-speed SerDes

SystemVerilog modelling

EM analysis

Education

MS/PhD in Electrical Engineering

Advanced CMOS design experience

Tools

Cadence EMX

Ansys HFSS

Job description

Upscale, Inc. is building world-class SerDes clocking for AI data centers. We seek a senior technical leader to define clocking architecture, PLLs, and distribution for 5nm CMOS, collaborating across analog, mixed-signal, digital, layout, and silicon validation teams.

You will drive architectural innovation, lead critical clocking development, and tackle jitter, coupling, and power-efficiency challenges. This role combines hands-on design with system-level verification and cross-functional