Senior Clocking Architect — Ultra-Low Jitter SerDes

Upscale; Kentucky; On-site; USD 180,000 - 270,000; Full time

Job summary

Upscale, Inc. is building the next generation of AI infrastructure and is seeking a senior clocking architecture leader for SerDes design.

You will define PLLs, clock generation, and distribution for 5nm and below processes, collaborating across analog, digital, layout, and silicon validation teams to achieve extreme timing performance. You will drive architectural innovation, tackle jitter and power-efficiency challenges, and deliver silicon-ready clocking solutions for 100G+ SerDes in a

Qualifications

• MS or PhD in Electrical Engineering or a related field.
• Extensive experience in high-performance analog and mixed-signal IC design.
• Proven ability to define clocking architectures and translate jitter requirements into specs.
• Experience with clock distribution design, coupling, skew, and power integrity.
• Hands-on experience with electromagnetic simulation and extraction tools.
• Experience developing SystemVerilog-based models and verification environments.
• Strong technical leadership and silicon delivery track record.
• Direct experience with clocking solutions for 100G+ SerDes.

Responsibilities

• Define and drive end-to-end clocking architecture for next-gen SerDes.
• Lead ultra-low-jitter PLL design targeting <100 fs RMS jitter.
• Develop hybrid, digital, and advanced PLL architectures and trade-offs.
• Mitigate coupling among multiple PLLs and clock-generation blocks.
• Define and implement resonant clock distribution to reduce power.
• Use EM simulation to optimize inductors, networks, and interconnects.
• Develop SystemVerilog models and verification environments for PLLs.
• Collaborate with TX/RX/ADC/digital/AMS layout teams to optimize link performance.
• Drive silicon execution, jitter analysis, and silicon correlation.

Job description

Upscale, Inc. is building the next generation of AI infrastructure and is seeking a senior clocking architecture leader for SerDes design.

You will define PLLs, clock generation, and distribution for 5nm and below processes, collaborating across analog, digital, layout, and silicon validation teams to achieve extreme timing performance. You will drive architectural innovation, tackle jitter and power-efficiency challenges, and deliver silicon-ready clocking solutions for 100G+ SerDes in a