Senior SerDes Clocking Architect — Ultra-Low Jitter PLLs

Upscale, Inc.; Kentucky; On-site; USD 313,000 - 353,000; Full time

Job summary

Upscale, Inc. is building high‑performance AI infrastructure and seeking a senior SerDes clocking leader to define the clocking architecture for next‑gen SerDes in 5nm and below.

You will own PLL design, latency, and jitter performance, coordinating across analog, mixed‑signal, digital, and layout teams to ensure robust, power‑efficient clocking solutions and successful silicon delivery.

Qualifications

• MS/PhD in EE with extensive high‑speed analog and mixed‑signal IC design.
• Proven success delivering ultra‑low‑jitter PLLs (100 fs class RMS) in 5nm or below CMOS.
• Ability to define clocking architectures and translate system jitter requirements to circuit specs.

Responsibilities

• Define end-to-end clocking architecture for next‑gen SerDes (PLLs, clock generation, distribution).
• Lead ultra‑low‑jitter PLL development targeting <100 fs RMS jitter in advanced CMOS.
• Evaluate hybrid and digital PLL architectures; trade‑offs among jitter, power, area, tuning range.
• Mitigate coupling among multiple PLLs and clocking blocks (supply, substrate, EMI).
• Define power‑efficient clock distribution, including resonant clocking techniques.
• Use EM tools to optimize inductors, resonant networks, and high‑frequency interconnects.
• Develop SystemVerilog models and verification environments for PLLs and clocking subsystems.
• Collaborate with SerDes TX/RX, ADC, digital, AMS layout, and silicon validation teams.
• Drive silicon execution, jitter analysis, and silicon correlation.

Skills

Ultra-low-jitter PLL design

PLL architecture & circuit design

Clocking architecture

Phase noise & jitter analysis

SystemVerilog models

Education

MS or PhD in Electrical Engineering or related field

Tools

Cadence EMX

Ansys HFSS

Job description

Upscale, Inc. is building high‑performance AI infrastructure and seeking a senior SerDes clocking leader to define the clocking architecture for next‑gen SerDes in 5nm and below.

You will own PLL design, latency, and jitter performance, coordinating across analog, mixed‑signal, digital, and layout teams to ensure robust, power‑efficient clocking solutions and successful silicon delivery.