Senior NoC Interconnect RTL Engineer – Relocation & Hybrid

OpenAI; San Francisco (CA); Hybrid; USD 130,000 - 180,000; Full time

Benefits offered by this job

Relocation assistance

Hybrid work model

Mentorship opportunities

Job summary

OpenAI is looking for a highly experienced RTL engineer to lead the design of critical on- and off-chip interconnect components for their custom AI accelerator platform. This senior role involves driving architecture through the silicon lifecycle, optimizing performance, and mentoring junior engineers.

The ideal candidate will have extensive experience in SoC design and RTL engineering, particularly in high-performance computing environments. The position offers a hybrid work model based in San Francisco, along with relocation assistance.

Qualifications

• 5+ years of experience in SoC design and RTL engineering.
• Strong understanding of memory subsystems and interconnect design.
• Ability to mentor and lead junior engineers.

Responsibilities

• Own the microarchitecture and RTL implementation of custom AI accelerator.
• Drive design and development through the silicon lifecycle.
• Collaborate with teams to optimize interconnect performance.

Skills

Verilog/SystemVerilog

Chip-level integration

Interconnect concepts

High-performance computing

Excellent communication skills

Education

Extensive industry experience

Tools

Performance analysis tools

Static timing analysis tools

Job description

OpenAI is looking for a highly experienced RTL engineer to lead the design of critical on- and off-chip interconnect components for their custom AI accelerator platform. This senior role involves driving architecture through the silicon lifecycle, optimizing performance, and mentoring junior engineers.

The ideal candidate will have extensive experience in SoC design and RTL engineering, particularly in high-performance computing environments. The position offers a hybrid work model based in San Francisco, along with relocation assistance.