Senior RTL Engineer: Interconnect & NoC Architect

OpenAI; California (MO); On-site; USD 140,000 - 200,000; Full time

Job summary

OpenAI is seeking a highly experienced RTL engineer to own critical on- and off-chip communication components for our AI accelerator platform. You will drive microarchitecture and SystemVerilog implementation of scalable NoC fabrics and packet-based interconnects, with production-facing responsibilities from verification to silicon bring-up.

The role expands to mentoring junior engineers, coordinating with architecture, performance, and post-silicon teams, and advancing interfaces and protocols

Qualifications

• Strong hands-on ownership of complex networking or interconnect RTL.
• Experience with Ethernet, NICs, RoCE, or NoC datapaths.
• Production-quality RTL with verification, linting, and timing analysis.

Responsibilities

• Own microarchitecture, RTL design, and delivery of interconnect components.
• Design routing, arbitration, QoS, and congestion management mechanisms.
• Develop on-chip/off-chip interfaces and protocol bridges for scale-out systems.
• Perform SystemVerilog coding, simulation, and debugging with verification teams.
• Collaborate with architecture and performance groups to optimize latency and bandwidth.
• Lead RTL delivery and mentor junior engineers across projects.
• Coordinate with firmware, software, and post-silicon teams through bring-up.
• Drive third-party engagements and ensure design quality and execution.

Skills

RTL design

SystemVerilog

NoC

Networking

HDL verification

Mentoring

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Verilog/VHDL simulators

Synthesis tools

Job description

OpenAI is seeking a highly experienced RTL engineer to own critical on- and off-chip communication components for our AI accelerator platform. You will drive microarchitecture and SystemVerilog implementation of scalable NoC fabrics and packet-based interconnects, with production-facing responsibilities from verification to silicon bring-up.

The role expands to mentoring junior engineers, coordinating with architecture, performance, and post-silicon teams, and advancing interfaces and protocols