Senior RTL Engineer: AI NoC & Networking Fabric

OpenAI; San Francisco (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

OpenAI is seeking a senior RTL engineer to own microarchitecture and RTL for high-bandwidth on‑chip fabrics and off‑chip interfaces. You will drive design from requirements through tape-out, mentoring juniors and coordinating with external partners.

The role emphasizes deep Verilog/SystemVerilog expertise, production-quality RTL, and strong collaboration across architecture, verification, and physical design to meet performance, power, and area targets.

Qualifications

• Hands-on ownership of complex networking or packet-switched RTL blocks.
• Production-quality RTL developed in Verilog/SystemVerilog.
• Experience with on-chip/off-chip interfaces (AXI/PCIe/CXL/Ethernet) and NoC fabrics.

Responsibilities

• Own microarchitecture, RTL design, and delivery of packet-based interconnect components.
• Design routing, arbitration, flow control, QoS, and scheduling mechanisms.
• Develop on-chip/off-chip interfaces and protocol extensions for scale-up systems.
• Conduct RTL coding, simulation, and debugging across large-scale datapaths.
• Collaborate with architecture, verification, and physical design teams to optimize latency and bandwidth.
• Lead verification planning, coverage, and debug strategies for highly concurrent fabric behavior.
• Mentor junior engineers and coordinate with external partners on IP integration.
• Provide technical direction and drive alignment while remaining hands-on in RTL work.

Skills

RTL ownership

Verilog/SystemVerilog

Networking/NoC design

Architectural leadership

Tools

SystemVerilog

Verilog

Job description

OpenAI is seeking a senior RTL engineer to own microarchitecture and RTL for high-bandwidth on‑chip fabrics and off‑chip interfaces. You will drive design from requirements through tape-out, mentoring juniors and coordinating with external partners.

The role emphasizes deep Verilog/SystemVerilog expertise, production-quality RTL, and strong collaboration across architecture, verification, and physical design to meet performance, power, and area targets.