Senior RTL Engineer – Memory-Centric IP for AI/ML

Samsungsemiconductor; San Jose (CA); On-site; USD 124,000 - 206,000; Full time

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Job summary

Samsung Semiconductor in San Jose, CA is seeking an experienced hardware IP designer to develop memory-centric computing IP using Verilog, SystemVerilog and HLS. You will optimize IP for performance, power, and area while collaborating with verification engineers on test plans and trade-off decisions across performance, power, and cost.

The role requires a strong microarchitecture background and 5+ years of front-end RTL design experience; you’ll work with AI/ML workloads and a team driving

Qualifications

• Develop IP for memory centric computing systems using Verilog, System Verilog and HLS.
• Optimize the IP for performance, power, and area by leveraging advanced design techniques such as pipelining, parallelism, and data compression.
• Collaborate with Verification engineers to design and develop test plans
• Make design decisions out of a large design trade-off space across performance, power, thermal, and cost.
• Troubleshoot and debug hardware issues and ensure the quality of the design through verification and validation.
• Stay up-to-date with the latest advancements in machine learning and hardware architecture and contribute to the development of new technologies.
• Communicate effectively with stakeholders, including users, partners, and management, to ensure that the systems are delivered on time and within budget
• Complete other responsibilities as assigned.

Responsibilities

• Develop IP for memory centric computing systems using Verilog, System Verilog and HLS.
• Optimize the IP for performance, power, and area by leveraging advanced design techniques such as pipelining, parallelism, and data compression.
• Collaborate with Verification engineers to design and develop test plans
• Make design decisions out of a large design trade-off space across performance, power, thermal, and cost.
• Troubleshoot and debug hardware issues and ensure the quality of the design through verification and validation.
• Stay up-to-date with the latest advancements in machine learning and hardware architecture and contribute to the development of new technologies.
• Communicate effectively with stakeholders, including users, partners, and management, to ensure that the systems are delivered on time and within budget
• Complete other responsibilities as assigned.

Skills

Microarchitecture

Computer architecture

RTL development

Memory Controller

NOC Interconnect IP

AI/ML workloads

Analytical skills

Communication skills

Teamwork

Independent work

Education

Bachelor's degree

Master's degree

PhD

Tools

Verilog

SystemVerilog

HLS

Job description

Samsung Semiconductor in San Jose, CA is seeking an experienced hardware IP designer to develop memory-centric computing IP using Verilog, SystemVerilog and HLS. You will optimize IP for performance, power, and area while collaborating with verification engineers on test plans and trade-off decisions across performance, power, and cost.

The role requires a strong microarchitecture background and 5+ years of front-end RTL design experience; you’ll work with AI/ML workloads and a team driving