Senior RTL Engineer — IO Die & Interconnect Architect

Samsung Semiconductor Inc.; San Jose (CA); On-site; USD 138,000 - 206,000; Full time

Benefits offered by this job

Medical/Dental/Vision/401k

4+ weeks of paid time off

Flexible work policy

Charitable giving match

Job summary

Samsung Semiconductor, Inc. in San Jose, CA is seeking an experienced RTL/SoC integration engineer to own the IO die architecture, interconnect IP, and chiplet interfaces for high-performance AI/ML workloads.

You will collaborate with architecture, verification, and software teams to optimize performance, power, and area for PCIe/CXL/UCIe based systems, delivering robust, scalable designs on schedule.

Qualifications

• Strong background in microarchitecture and RTL design for complex SoC and die integration.
• 5+ years RTL development experience for high-speed interconnect subsystems.
• Experience integrating PCIe, CXL, UCIe and die-to-die interfaces.
• Experience modifying third-party interconnect IP for die-level requirements.
• Familiarity with chiplet-based multi-die architectures and die-to-die interconnect.
• Understanding of PCIe/CXL protocol stacks and PIPE interface.
• Experience with SoC integration methodologies and IP packaging (AXI/ACE/CHI/APB).
• Proficient in scripting for design automation; AI tools a plus.
• Experience in AI/ML workloads.
• Strong analytical and communication skills.

Responsibilities

• Develop RTL for the IO die, integrating UCIe, PCIe, and other interconnect IP.
• Integrate internal and third-party interconnect IP into the IO die, including configuration and glue logic.
• Modify PCIe and other interconnect IP to meet die-level requirements.
• Define and implement die-to-die and chiplet interfaces using UCIe.
• Own the microarchitecture and RTL for IO subsystems like PCIe/CXL controllers.
• Collaborate with verification engineers to develop test plans and debug issues.
• Work with architecture, PHY/SerDes, physical design, and software teams to close requirements.
• Make design decisions across performance, power, latency, bandwidth, cost.
• Develop and automate IP integration and RTL assembly flows using scripting and AI tools.
• Communicate with stakeholders to ensure delivery on time and within budget.
• Complete other responsibilities as assigned.

Skills

RTL design Verilog/SystemVerilog

SoC integration

PCIe/CXL/UCIe interconnect

Scripting (Tcl/Python/Perl)

AI/ML workloads

Team collaboration

Analytical thinking

Communication skills

Chiplet architecture

Die-to-die interfaces

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in a relevant field

Tools

IP-XACT

Job description

Samsung Semiconductor, Inc. in San Jose, CA is seeking an experienced RTL/SoC integration engineer to own the IO die architecture, interconnect IP, and chiplet interfaces for high-performance AI/ML workloads.

You will collaborate with architecture, verification, and software teams to optimize performance, power, and area for PCIe/CXL/UCIe based systems, delivering robust, scalable designs on schedule.