Senior RTL Engineer: Memory-Centric AI/ML IP

Socket.dev; San Jose (CA); On-site; USD 138,000 - 206,000; Full time

Benefits offered by this job

Charitable giving match

Paid time off 4+ weeks

Fertility/adoption stipend

Medical/dental/vision

Wellness & mental health support

Onsite cafe and gym

Job summary

Samsung Semiconductor in San Jose, CA is seeking a senior hardware architect to develop memory-centric IP for AGI computing workloads. You will collaborate with Verilog/SystemVerilog and HLS to optimize IP for performance, power, and area, and work with verification teams to create robust test plans.

Applicants should have 5+ years in microarchitecture and RTL design, plus memory controller/NOC experience and a track record in AI/ML workloads.

Qualifications

• Bachelor’s with 5+ years, or Master’s with 3+ years, or PhD's with 0+ years of industry experience.
• Strong background in microarchitecture and computer architecture.
• 5+ years of experience in front-end design methodology involving RTL development for complex control and data path IPs.
• Experience in Memory Controller, NOC, Interconnect IP.
• Experience in Memory Centric computing IP and SOC integration.
• Experience in AI/ML workloads.

Responsibilities

• Develop IP for memory centric computing systems using Verilog, SystemVerilog and HLS.
• Optimize the IP for performance, power, and area by leveraging advanced design techniques.
• Collaborate with Verification engineers to design and develop test plans.
• Make design decisions across a large design trade-off space.
• Troubleshoot and debug hardware issues and ensure design quality through verification.
• Stay up-to-date with advancements in machine learning and hardware architecture.
• Communicate with stakeholders to ensure on-time delivery within budget.

Skills

Microarchitecture

Computer architecture

Analytical problem solving

Communication skills

Teamwork

Education

Bachelor's degree

Master's degree

PhD

Tools

RTL development

Memory controller design

NOC/IP design

Job description

Samsung Semiconductor in San Jose, CA is seeking a senior hardware architect to develop memory-centric IP for AGI computing workloads. You will collaborate with Verilog/SystemVerilog and HLS to optimize IP for performance, power, and area, and work with verification teams to create robust test plans.

Applicants should have 5+ years in microarchitecture and RTL design, plus memory controller/NOC experience and a track record in AI/ML workloads.