Senior RTL Engineer — Low-Power CPU Design

Google LLC; Mountain View (CA); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Equity

Bonus target 15%

Job summary

Google LLC in Mountain View, CA seeks a senior engineer to push the boundaries of custom silicon that powers Google's consumer products. You will shape next-gen hardware experiences with a focus on performance, efficiency, and integration across CPU, RTL, and power domains.

The role emphasizes in-person collaboration, advanced power modeling, and close work with SoC teams to deliver cutting-edge energy-efficient silicon solutions.

Qualifications

• Bachelor's degree in electrical/computer engineering or related field, or equivalent practical experience.
• 8 years of RTL design experience using Verilog or SystemVerilog.
• Experience with low-power digital design methodologies.

Responsibilities

• Own and drive activities related to CPU architecture and system-level energy modeling, and conduct power analysis for performance and efficiency.
• Develop novel power analysis techniques and tooling to improve battery life estimation and energy efficiency of CPUs.
• Perform RTL and gate-level data mining to define micro-architectural transactions for high-level power estimation.
• Collaborate with the SoC and CPU Power Team on power projections and workload profiling for high-traffic workloads.
• Perform workload analysis for battery life and define tests for power analysis and optimization.

Skills

RTL design (Verilog/SV)

Low-power design

CPU benchmarking

Power management

Education

Bachelor's degree in EE/CE/CS or related field

Tools

PTPX

Ansys Power Artist

Synopsys Prime Power

Job description

Google LLC in Mountain View, CA seeks a senior engineer to push the boundaries of custom silicon that powers Google's consumer products. You will shape next-gen hardware experiences with a focus on performance, efficiency, and integration across CPU, RTL, and power domains.

The role emphasizes in-person collaboration, advanced power modeling, and close work with SoC teams to deliver cutting-edge energy-efficient silicon solutions.