RTL Engineer — IO Die & Chiplet Interconnect

Socket.dev; San Jose (CA); On-site; USD 138,000 - 206,000; Full time

Benefits offered by this job

4+ weeks paid vacation

Medical/Dental/Vision/401k

Charitable giving match

Fertility/adoption stipend

Mental health support (therapy)

Onsite Café and gym

Flexible work environment

Job summary

Samsung Semiconductor is seeking a senior RTL/SoC integration engineer in San Jose to develop and integrate IO die architectures using UCIe, PCIe, and related IP. You will own microarchitecture and RTL for IO subsystems while collaborating with verification, architecture, and software teams.

Qualifications include 5+ years in RTL development and hands-on experience with PCIe/CXL/UCIe interconnects, die-to-die interfaces, and scripting.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 5+ years of RTL development and SoC/interconnect experience.
• Experience with PCIe/CXL/UCIe interconnects and die-to-die interfaces.

Responsibilities

• Develop RTL (Verilog/SystemVerilog) for IO die integrating UCIe, PCIe, and other interconnect IP.
• Modify PCIe/CXL IP and implement die-to-die and chiplet interfaces.
• Collaborate with verification, architecture, PHY/SerDes, and software teams to meet requirements.
• Own microarchitecture and RTL for IO subsystems and provide test plans.

Skills

RTL Verilog

Microarchitecture

Interconnect IP

Scripting

AI/ML workloads

Communication

Teamwork

Chiplet architecture

Die-to-die interfaces

Education

Bachelors in Electrical Engineering or related field

Masters in EE/CS (preferred)

Tools

PCIe

CXL

UCIe

IP-XACT

AXI/ACE/CHI/APB

Job description

Samsung Semiconductor is seeking a senior RTL/SoC integration engineer in San Jose to develop and integrate IO die architectures using UCIe, PCIe, and related IP. You will own microarchitecture and RTL for IO subsystems while collaborating with verification, architecture, and software teams.

Qualifications include 5+ years in RTL development and hands-on experience with PCIe/CXL/UCIe interconnects, die-to-die interfaces, and scripting.