Silicon RTL Tech Lead for AI Interconnect

Astera Labs; San Jose (CA); On-site; USD 133,000 - 185,000; Full time

Job summary

Astera Labs is seeking a Tech Lead Design Engineer to own RTL design for critical connectivity blocks powering AI infrastructure. You will drive from microarchitecture to tapeout, delivering synthesizable Verilog/SystemVerilog with emphasis on timing, CDC, and low-power strategies.

You will collaborate across architecture, verification, DFT, and physical design to ensure robust, scalable silicon while mentoring junior engineers and contributing to design methodology.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related field.
• 5+ years of digital design experience including at least one full chip from spec to tapeout.
• Proficiency in Verilog/SystemVerilog, RTL coding and synthesis flows.
• Experience with timing closure, CDC, lint and low-power design techniques.
• Solid understanding of high-speed serial interfaces (PCIe, Ethernet) and SoC integration.

Responsibilities

• Own RTL design for assigned blocks from microarchitecture through synthesis sign-off.
• Develop high-quality, synthesizable Verilog/SystemVerilog with focus on PPA.
• Drive design reviews, lint, CDC, and timing closure to silicon-ready quality.
• Translate specifications into implementation-ready microarchitecture with architecture team.
• Collaborate with verification on test plans, coverage closure, and bug triage.
• Mentor junior engineers and contribute to design methodology, scripts, and best practices.
• Debug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation.

Skills

Verilog/SystemVerilog

RTL coding

Timing closure

CDC / lint

Low-power design

High-speed interfaces (PCIe/Ethernet)

Education

Bachelor's degree in Electrical/Computer Engineering or related field

MS or PhD in Electrical/Computer Engineering

Tools

EDA tools

Formal verification tools

Emulation environments

Job description

Astera Labs is seeking a Tech Lead Design Engineer to own RTL design for critical connectivity blocks powering AI infrastructure. You will drive from microarchitecture to tapeout, delivering synthesizable Verilog/SystemVerilog with emphasis on timing, CDC, and low-power strategies.

You will collaborate across architecture, verification, DFT, and physical design to ensure robust, scalable silicon while mentoring junior engineers and contributing to design methodology.