Power & Clocking RTL Design Engineer - RISC-V SoC

SiFive, Inc.; Boston (MA); On-site; USD 140,000 - 210,000; Full time

Job summary

SiFive, Inc. in Boston, MA, seeks a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer to shape the central nervous system for high‑performance RISC-V CPU and SoC IP. You will design power, reset, and clocking solutions for configurable hardware blocks with the speed of software.

Join a team that values collaboration across architecture, verification, physical design and software to deliver high‑quality IP quickly, balancing area, power and performance.

Qualifications

• 3+ years in CPU and SoC clocking, reset, and power-management logic designs.
• Experience in high-performance, energy-efficient CPU and SoC designs.
• Proficiency with RTL languages: Verilog/SystemVerilog.
• BS/MS in EE, CE, CS or related technical discipline.

Responsibilities

• Define power management, reset and clocking requirements with the architecture team.
• Architect, design and implement core clocking, reset and power management solutions.
• Develop microarchitecture, document clearly and share knowledge.
• Perform initial sandbox verification and work with verification teams on test plans.
• Collaborate with physical implementation to meet frequency, area and power goals.
• Coordinate with software teams to enable and optimize power management features.

Skills

CPU design

RTL design

Verilog/SystemVerilog

DVFS

Power management

Clocking

Collaboration

Education

BS in EE/CE/CS

MS in EE/CE/CS

Tools

Spyglass

RTL verification tools

Job description

SiFive, Inc. in Boston, MA, seeks a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer to shape the central nervous system for high‑performance RISC-V CPU and SoC IP. You will design power, reset, and clocking solutions for configurable hardware blocks with the speed of software.

Join a team that values collaboration across architecture, verification, physical design and software to deliver high‑quality IP quickly, balancing area, power and performance.