Senior RTL Design Engineer - RISC-V Core & Chisel Architect

SiFive; Santa Clara (CA); On-site; USD 159,000 - 194,000; Full time

Job summary

SiFive is seeking a CPU design engineer in Santa Clara to architect and implement RISC-V core features and extensions, using Chisel/FIRRTL. You will help integrate design content and enhance verification/testbenches while collaborating with multiple teams to deliver optimized, high-quality cores.

The role demands 3+ years in CPU RTL design, proficiency in Verilog/SystemVerilog, and a strong software engineering background. A collaborative, detail-oriented mindset is essential for success.

Qualifications

• BS/MS in CS/CE/EE or related field, or equivalent experience.
• 3+ years of design experience.
• CPU RTL design experience: fetch, decode, branch prediction, caches, TLBs.
• RTL design proficiency: Verilog, SystemVerilog, or VHDL.
• Strong software engineering background: OO/FP, templated metaprogramming, compiler infrastructure, data modeling, test-driven development.
• Attention to detail and ability to work in a collaborative team.

Responsibilities

• Architect, design and implement features, performance improvements, and ISA extensions in RISC-V core generators using Chisel.
• Integrate design content into Chisel/FIRRTL framework and improve tooling for docs/tests and packaged software.
• Perform initial sandbox verification with the verification team for test plans.
• Work with physical implementation to optimize design for frequency, area and power.
• Collaborate with performance modeling for exploration and optimization.
• Document knowledge and contribute to a culture of collaborative design.

Skills

Verilog/SystemVerilog

Software engineering

Functional programming

Compiler infrastructures

Test-driven development

Teamwork

Education

BS/MS in CS/CE/EE or related field

Tools

Git/Github

Jira

Confluence

Job description

SiFive is seeking a CPU design engineer in Santa Clara to architect and implement RISC-V core features and extensions, using Chisel/FIRRTL. You will help integrate design content and enhance verification/testbenches while collaborating with multiple teams to deliver optimized, high-quality cores.

The role demands 3+ years in CPU RTL design, proficiency in Verilog/SystemVerilog, and a strong software engineering background. A collaborative, detail-oriented mindset is essential for success.