Sr. RTL Design Engineer (Silicon Engineering)

SPACE EXPLORATION TECHNOLOGIES CORP; Irvine (CA); On-site; USD 160,000 - 225,000; Full time

Benefits offered by this job

Comprehensive medical, vision, and dental coverage

401(k) retirement plan

Paid parental leave

3 weeks paid vacation

10 or more paid holidays per year

Job summary

SPACE EXPLORATION TECHNOLOGIES CORP in Irvine, CA, is seeking a Sr. RTL Design Engineer to develop cutting-edge ASICs for deployment in space and ground infrastructures. This role requires 5+ years of RTL implementation experience and a Bachelor’s degree in Electrical Engineering or Computer Engineering.

The engineer will work cross-disciplinarily to maximize the utility of the Starlink network and must be proactive and intellectually curious. Excellent problem-solving and collaboration skills are essential.

Competitive compensation includes a salary range of $160,000 - $225,000 per year, plus benefits and stock options.

Qualifications

• 5+ years of experience in RTL implementation.

Responsibilities

• Evaluate architectural trade‑offs based on features, performance requirements and system limitations.
• Define micro‑architecture and implement RTL in Verilog/System Verilog.
• Work closely with verification team to ensure design is covered and verified.
• Provide timing constraints and support physical implementation team.
• Participate in silicon bring‑up and validation.

Skills

Problem-solving

Team collaboration

Clock domain crossings

Power optimization

High speed design techniques

Low power design techniques

Education

Bachelor’s degree in electrical engineering, computer engineering, or computer science

Tools

HDL simulators

HDL Lint tools

Job description

SR. RTL DESIGN ENGINEER (SILICON ENGINEERING)

Irvine, CA

SpaceX was founded under the belief that a future where humanity explores the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best‑in‑class engineers to help maximize Starlink’s utility for communities and businesses around the globe.

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world‑class cross‑disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting‑edge next‑generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting‑edge solutions that will expand the performance and capabilities of the Starlink network.

Responsibilities

• Evaluate architectural trade‑offs based on features, performance requirements and system limitations
• Define micro‑architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design
• Work closely with verification team to ensure all aspects of the design are covered and verified
• Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check)
• Participate in silicon bring‑up and validation

Basic Qualifications

• Bachelor’s degree in electrical engineering, computer engineering, or computer science
• 5+ years of experience in RTL implementation

Preferred Skills and Experience

• Ability to solve complex problems including clock domain crossings and power optimization
• Experience with embedded CPU subsystems
• Experience with standard bus protocols (e.g. AXI, AHB, etc.)
• Experience with high speed and low power design techniques
• Experience with EDA tools such as HDL simulators and HDL Lint tools
• Team‑player, can‑do attitude and ability to work well in a group environment while still contributing on an individual basis
• Enjoys being challenged and learning new skills

Additional Requirements

• Ability to work extended hours or weekends as needed for mission critical deadlines
• To conform to U.S. Government export regulations, applicant must be a U.S. citizen, lawful permanent resident (green card holder), Refugee under 8 U.S.C. § 1157, or Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.

Compensation & Benefits

Pay range: ASIC Design Engineer/Senior: $160,000.00 - $225,000.00 per year.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long‑term incentives, in the form of company stock, stock options, or long‑term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long‑term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.