Senior RTL Design Engineer – Edge AI & Low-Power SoC

present of AI; San Francisco, Pittsburgh, Austin (CA, Allegheny County, TX); On-site; USD 180,000 - 240,000; Full time

Job summary

Efficient Computer in San Francisco (also listed for Bay Area, Pittsburgh, PA and Austin, TX) seeks a senior RTL design engineer to own block level design, integration and sign-off for complex SoC components. You should bring strong Verilog or SystemVerilog, timing closure and low‑power techniques, plus familiarity with on‑chip interconnect and memory interfaces.

Work focuses on hardware that runs AI models with very low power for edge devices.

Qualifications

• Hands-on experience with RTL design for complex SoCs.
• Proficiency in Verilog or SystemVerilog.
• Strong timing closure and low-power techniques.

Responsibilities

• Own block level design, integration and sign-off for complex SoC components.
• Apply Verilog/SystemVerilog skills to ensure timing closure and robustness.
• Leverage low-power techniques and memory interface knowledge in daily work.

Skills

RTL design

RTL integration

Sign-off

Verilog

SystemVerilog

Timing closure

Low power

On-chip interconnect

Memory interfaces

Job description

Efficient Computer in San Francisco (also listed for Bay Area, Pittsburgh, PA and Austin, TX) seeks a senior RTL design engineer to own block level design, integration and sign-off for complex SoC components. You should bring strong Verilog or SystemVerilog, timing closure and low‑power techniques, plus familiarity with on‑chip interconnect and memory interfaces.

Work focuses on hardware that runs AI models with very low power for edge devices.