Senior RTL Design Engineer – DRAM Digital Circuits

Micron Technology Inc; Boise (ID); Hybrid; USD 120,000 - 160,000; Full time

Benefits offered by this job

Medical plans

Paid time off

Paid holidays

Job summary

Micron Technology Inc. in Boise, Idaho seeks a Design Engineer to own RTL design for DRAM‑related digital circuits, drive STA and timing closure, and collaborate with verification, product engineering, and manufacturing teams to deliver robust designs.

The role emphasizes hands‑on RTL ownership, optimization, and cross‑functional collaboration in a hybrid work environment, contributing to product quality and time‑to‑market.

Qualifications

• Bachelor’s degree in Electrical Engineering or equivalent practical experience.
• 6+ years of experience in digital or RTL circuit design.
• Strong experience with RTL design, STA, and timing closure.
• Experience with power delivery network circuit design and optimization.
• Proficiency in UNIX and Cadence design environments.

Responsibilities

• Design and optimize RTL for DRAM‑related digital circuits and block‑level designs.
• Perform STA and drive timing closure across critical paths.
• Collaborate with verification, product engineering, test, and process teams to ensure robust designs.
• Support circuit verification, layout checks, and parasitic extraction analysis.

Skills

RTL design

STA

Timing closure

Power delivery design

UNIX

Cadence environments

Education

Bachelor’s degree in Electrical Engineering

Master’s degree in Electrical Engineering

Tools

Cadence design environments

IC compilers

Synthesis tools

Job description

Micron Technology Inc. in Boise, Idaho seeks a Design Engineer to own RTL design for DRAM‑related digital circuits, drive STA and timing closure, and collaborate with verification, product engineering, and manufacturing teams to deliver robust designs.

The role emphasizes hands‑on RTL ownership, optimization, and cross‑functional collaboration in a hybrid work environment, contributing to product quality and time‑to‑market.