Senior Logic Design Engineer - Hybrid Datacenter RTL

Intel Corporation; Santa Clara (CA); Hybrid; USD 141,910 - 200,340; Full time

Benefits offered by this job

Hybrid work model

Health benefits

Retirement plan

Paid vacation

Job summary

Intel Corporation's HIPD team seeks a senior Logic design engineer to advance the UCIE PHY IP for datacenter/server designs. You will craft RTL, simulate, and contribute to architecture definitions for the IP block.

Responsibilities include RTL quality checks, timing and power convergence, and design optimization for performance, area, and reliability. Collaboration across organizations is essential for success.

Qualifications

• RTL/Logic design using SystemVerilog for IP blocks.
• Data path, power-management flow, arbitration logic, CDC, and state machines.
• Front End tools for lint and synthesis; hardware simulation with VCS/Verdi.

Responsibilities

• Develop RTL and RTL coding with RTL verification.
• Define architecture and microarchitecture features for the block.
• Perform RTL-to-timing/power convergence quality checks.

Skills

RTL/Verilog

SystemVerilog

VCS

Verdi

Lint & Synthesis

Clock Domain Crossing

UPF

Power management

State machines

Arbitration logic

Education

Bachelor's degree in Electrical or Computer Engineering

Master's degree in Electrical or Computer Engineering

PhD in Electrical or Computer Engineering

Tools

VCS

Verdi

Lint tools

Synthesis tools

Job description

Intel Corporation's HIPD team seeks a senior Logic design engineer to advance the UCIE PHY IP for datacenter/server designs. You will craft RTL, simulate, and contribute to architecture definitions for the IP block.

Responsibilities include RTL quality checks, timing and power convergence, and design optimization for performance, area, and reliability. Collaboration across organizations is essential for success.