Sr. Logic Design Engineer

Intel; Phoenix (AZ); Hybrid; USD 141,910 - 200,340; Full time

Job summary

Intel's HIPD team is seeking a senior Logic design engineer to join the UCIE PHY IP for flagship datacenter/server designs.

You will design RTL, contribute to architecture, perform quality checks, optimize for power, timing and area, and ensure verification of features. This role offers a hybrid work model with locations in Santa Clara and Phoenix, and competitive compensation.

Qualifications

• Candidate must possess a Bachelor's degree in Electrical or Computer Engineering or related field with 4+ years of experience.
• Alternative: Master’s degree with 2+ years or PhD with 1+ year in related field.

Responsibilities

• Develops the logic design, register transfer level (RTL) coding, and simulation for IP block.
• Participates in the definition of architecture and microarchitecture features of the block being designed.
• Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence.
• Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
• Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.

Skills

RTL/Verilog design

Data path design

Power management

Arbitration logic

Clock Domain Crossing

State machines

UPF

Education

Bachelor's degree in Electrical or Computer Engineering

Master's degree in Electrical or Computer Engineering

PhD in Electrical or Computer Engineering

Tools

VCS

Verdi

Lint

Synthesis

Job description

• RTL/Logic design using System Verilog Language

Job Details

Job Description: Intel's HIPD team is looking for an experienced senior Logic design engineer to join the rapidly growing UCIE PHY IP for Intel's flagship datacenter/server designs.

Responsibilities Will Include But Not Limited To

• Develops the logic design, register transfer level (RTL) coding, and simulation for IP block.
• Participates in the definition of architecture and microarchitecture features of the block being designed.
• Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence.
• Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
• Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.

Behavior Skills We Are Looking For

• Excellent written and oral presentation skills, and willing to work across multiple organizations and geographies.
• Effective team player with continuous learning mindset.
• Strong analytical and problem-solving skills.
• Be willing to balance multiple tasks.
• Ramp quickly on new and complex IPs in a dynamic environment is critical.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

Candidate must possess a Bachelor's degree in Electrical or Computer Engineering or a related field and 4+ years' experience OR a Master's degree in Electrical or Computer Engineering or a related field and 2+ years' experience OR a PhD in Electrical or Computer Engineering or a related field and 1+ years' experience.

Relevant Work Experience Must Be In

• RTL/Logic design using System Verilog Language
• Experience with Design of Data path, Power-management flow, Arbitration logic, Clock Domain Crossing, State Machines, UPF
• Experience with Front End design tools for Lint, Synthesis.
• Experience with hardware simulation tools and methodologies (VCS/Verdi).
• Familiarity with IP environment and configuration management tools.

Preferred Qualifications

• UCIE PHY Design and Mixed-Signal Environment.
• Cross Domain Crossing, Voltage Domain Crossings,

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Job Type

Experienced Hire

Shift

Shift 1 (United States of America)

Primary Location

US, California, Santa Clara

Additional Locations

US, Arizona, Phoenix, US, Oregon, Hillsboro

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $141,910.00 - 200,340.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.