Senior SystemVerilog RTL Design Engineer – IP/PHY

Intel; Santa Clara (CA); Hybrid; USD 141,910 - 200,340; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Retirement plan

Vacation

Job summary

Intel's HIPD team seeks a senior Logic design engineer for UCIE PHY IP in datacenter/server designs. You will develop RTL, define architecture features, and ensure design quality from RTL to timing convergence.

The role requires strong SystemVerilog expertise, collaboration across geographies, and a fast ramp on complex IPs in a dynamic environment. Hybrid work model offered in the US.

Qualifications

• Requires degree in electrical/computer engineering with relevant experience.
• Experience RTL/Verilog design and front-end tools is essential.
• Knowledge of IP/UCIE PHY environments is a plus.

Responsibilities

• Develops RTL, RTL coding, and simulation for IP blocks.
• Contributes to architecture/microarchitecture feature definition.
• Performs quality checks from RTL to timing/power convergence.
• Optimizes logic to meet power, performance, area, and timing goals.
• Reviews verification plans and fixes RTL test failures.

Skills

RTL/Logic design

SystemVerilog

Data path design

Clock Domain Crossing

Collaboration

Education

Bachelor's degree in Electrical or Computer Engineering

Master's degree in Electrical or Computer Engineering

PhD in Electrical or Computer Engineering

Tools

VCS/Verdi

Lint & Synthesis tools

Job description

Intel's HIPD team seeks a senior Logic design engineer for UCIE PHY IP in datacenter/server designs. You will develop RTL, define architecture features, and ensure design quality from RTL to timing convergence.

The role requires strong SystemVerilog expertise, collaboration across geographies, and a fast ramp on complex IPs in a dynamic environment. Hybrid work model offered in the US.