Senior RTL Design Engineer for High-Throughput ASIC/SoC

Wipro Ltd.; San Diego (CA); On-site; USD 80,000 - 160,000; Full time

Benefits offered by this job

Medical and dental benefits

Disability insurance

Paid time off

Job summary

Wipro Limited in California is seeking an experienced ASIC/SoC Design Engineer to deliver high-throughput, low-latency data transport architectures. The role emphasizes RTL coding in Verilog/SystemVerilog and seamless integration with digital design flows.

Applicants should have 8+ years in ASIC/SOC design with a proven tape-out track record in deep sub-micron technologies. You will work with PD engineers to optimize performance, area and power, particularly for arbitration and fabric logics.

Qualifications

• 8+ years of experience delivering ASIC/SOC designs for high-throughput/low-latency data transport.
• 8+ years in Digital Design with RTL coding using Verilog/SystemVerilog.
• Experience with RTL2PD tool/flow setup and debugging.
• Strong collaboration with PD engineers for architecture tradeoffs.

Responsibilities

• Deliver ASIC/SOC designs for arbitration and fabric logics.
• Work on high-throughput/low-latency data transport architectures.
• Collaborate with PD engineers to optimize performance, area and power.
• Lead tape-out efforts in deep sub-micron technologies.

Skills

RTL coding

Verilog/SystemVerilog

AXI

Timing constraints

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Lint

CDC

RDC

VCLP

Synthesis

FEV

Job description

Wipro Limited in California is seeking an experienced ASIC/SoC Design Engineer to deliver high-throughput, low-latency data transport architectures. The role emphasizes RTL coding in Verilog/SystemVerilog and seamless integration with digital design flows.

Applicants should have 8+ years in ASIC/SOC design with a proven tape-out track record in deep sub-micron technologies. You will work with PD engineers to optimize performance, area and power, particularly for arbitration and fabric logics.