Senior ASIC RTL Design Engineer AI Hardware (Hybrid/Remote)

RiseMe; Sunnyvale (CA); Hybrid; USD 200,000 - 290,000; Full time

Job summary

Cerebras Systems seeks a senior front-end design engineer to drive RTL design and integration for the Wafer Scale Engine. You will work with verification, physical design, software and system teams to bring innovative architectures from concept to production.

The role demands 8+ years of RTL experience, hybrid work capability, and a track record of silicon successes. Collaboration with external vendors and exposure to high-performance computing are essential.

Qualifications

• Master’s degree in Computer Science, Electrical Engineering, or equivalent.
• 8+ years of experience delivering complex RTL designs.
• Hybrid work environment available.
• Experience with Front End Chip integration and third-party IP integration.
• Experience in high-performance computing, GPU/CPU designs, machine learning or related fields.
• Proven track record of multiple silicon successes.
• Experience collaborating with external vendors.
• Networking stack experience including TCP/IP, RDMA and Ethernet.
• Knowledge of PCIe, CPU interfaces and Serdes technology.
• Working knowledge of scripting tools: Python, TCL.

Responsibilities

• Drive all aspects of chip design including Functional Specification, Micro-architecture, RTL development, Synthesis.
• Collaborate with PD team for design closure to meet PPA goals.
• Coordinate with Design verification and DFT teams for functional and test coverage.
• Partner with software and system teams to deliver optimal performance and feature set.
• Debug silicon-level functional, timing, and power issues during bring up.

Skills

RTL design

Synthesis

Front End Chip integration

Third-party IP integration

Python

TCL

Networking (TCP/IP, RDMA, Ethernet)

PCIe knowledge

CPU/GP U architectures

External vendor collaboration

Education

Master's degree in Computer Science, Electrical Engineering, or equivalent

Tools

Place and Route

Floor planning

Timing Analysis

Job description

Cerebras Systems seeks a senior front-end design engineer to drive RTL design and integration for the Wafer Scale Engine. You will work with verification, physical design, software and system teams to bring innovative architectures from concept to production.

The role demands 8+ years of RTL experience, hybrid work capability, and a track record of silicon successes. Collaboration with external vendors and exposure to high-performance computing are essential.