Senior RTL/ASIC Design Engineer: High-Speed Interfaces

MaC VC

San Diego (CA)

On-site

USD 146,000 - 218,000

Full time

8 days ago

Get a reply from this employer

Your resume and cover letter, tailored to exactly what they’re hiring for.

Get past ATS filters

Job summary

Qualcomm Technologies, Inc. is seeking seasoned digital design engineers to architect and implement high-performance mixed-signal IP blocks such as SerDes, DDR, and die-to-die interfaces.

You will collaborate with system architecture and analog teams from RTL through GDSII to deliver optimized ASIC designs. The role requires strong RTL/ASIC expertise, 7+ years in the field, and experience with front-end tools like VCS, Fusion Compiler, and PrimeTime.

Qualifications

  • Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • 7+ years of RTL and ASIC design experience is required.
  • Experience with mixed-signal IPs such as SerDes, DDR PHY, PLLs, DACs, ADCs is preferred.
  • Proficiency with industry-standard front-end ASIC design tools: VCS, Fusion Compiler, PrimeTime.

Responsibilities

  • Architect and define the digital design of high-speed interface IPs (SerDes, DDR, die-to-die).
  • Develop micro-architecture and RTL for complex mixed-signal IPs.
  • Enhance power, performance, and area through advanced techniques.
  • Perform HDL linting, CDC analysis, DFT, synthesis, FV, and STA.
  • Create comprehensive design documentation and test plans.

Skills

RTL design
ASIC design
Digital design
SerDes
DDR PHY
PCIe/USB/UFS
PPA optimization

Education

Master’s degree in Electrical Engineering or Computer Engineering
PhD in Electrical Engineering

Tools

VCS
Fusion Compiler
PrimeTime
Power Compiler
DFT Compiler
Spyglass

Job description

Qualcomm Technologies, Inc. is seeking seasoned digital design engineers to architect and implement high-performance mixed-signal IP blocks such as SerDes, DDR, and die-to-die interfaces.

You will collaborate with system architecture and analog teams from RTL through GDSII to deliver optimized ASIC designs. The role requires strong RTL/ASIC expertise, 7+ years in the field, and experience with front-end tools like VCS, Fusion Compiler, and PrimeTime.

Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

Senior ASIC RTL Design Engineer — High-Speed Interfaces
Senior ASIC RTL Design Engineer — High-Speed Interfaces

Anysilicon • San Diego (CA)

Hybrid
USD 120,000 - 190,000
Senior ASIC RTL & Mixed-Signal IP Designer
Senior ASIC RTL & Mixed-Signal IP Designer

Qualcomm • San Diego (CA)

On-site
USD 140,000 - 210,000
Senior ASIC RTL & Mixed-Signal IP Architect
Senior ASIC RTL & Mixed-Signal IP Architect

QUALCOMM, Inc. • San Diego (CA)

On-site
USD 140,000 - 210,000
ASIC/RTL Design Engineer for High-speed Interfaces
ASIC/RTL Design Engineer for High-speed Interfaces

Anysilicon • San Diego (CA)

Hybrid
USD 120,000 - 190,000
ASIC RTL Design Engineer - High-Performance SoC
ASIC RTL Design Engineer - High-Performance SoC

QUALCOMM, Inc. • San Diego (CA)

On-site
USD 101,000 - 152,000
Senior ASIC Design Engineer – High-Speed Memory & Cache
Senior ASIC Design Engineer – High-Speed Memory & Cache

Qualcomm • San Diego (CA)

On-site
USD 101,000 - 152,000
ASIC/RTL Design Engineer for High-speed Interfaces
ASIC/RTL Design Engineer for High-speed Interfaces

Qualcomm • San Diego (CA)

On-site
USD 140,000 - 210,000
ASIC/RTL Design Engineer for High-speed Interfaces
ASIC/RTL Design Engineer for High-speed Interfaces

QUALCOMM, Inc. • San Diego (CA)

On-site
USD 140,000 - 210,000
ASIC Design Engineer - IP/SoC Architect
ASIC Design Engineer - IP/SoC Architect

WarmStart Ltd • Santa Clara (CA)

Hybrid
USD 120,000 - 150,000
ASIC/RTL Design Engineer for High-speed Interfaces
ASIC/RTL Design Engineer for High-speed Interfaces

MaC VC • San Diego (CA)

On-site
USD 146,000 - 218,000