Senior RTL Architect Engineer — Remote IP & Micro-Arch

Experis (Austria); San Francisco (CA); Remote; USD 83.000 - 118.000; Vollzeit

Zusammenfassung

Experis (Austria) seeks an RTL Designer Engineer for a 6-month remote engagement in San Francisco, CA. The role requires 8–15 years of RTL design experience and strong SystemVerilog/Verilog expertise.

You will own micro-architecture definitions, develop RTL for complex digital blocks, and coordinate IP integration while supporting sign-off activities (CDC, RDC, lint, synthesis). Collaboration with DV teams is essential.

Qualifikationen

• 8-15 years of RTL design experience
• Strong SystemVerilog/Verilog expertise
• Experience defining micro-architecture independently
• Familiarity with sign-off flows including CDC and RDC
• Ability to operate with minimal supervision

Aufgaben

• Own micro-architecture definition from high-level functional specifications
• Develop and implement RTL for complex digital blocks
• Drive digital block control and IP integration
• Participate in subsystem-level architecture alignment
• Support design sign-off activities (CDC, RDC, lint, synthesis readiness)
• Collaborate closely with DV for closure and debug

Kenntnisse

RTL design

SystemVerilog/Verilog

IP integration

Memory subsystems

Ausbildung

MS in CS or EE

Tools

CDC tooling

Lint/synthesis tooling

Jobbeschreibung

Experis (Austria) seeks an RTL Designer Engineer for a 6-month remote engagement in San Francisco, CA. The role requires 8–15 years of RTL design experience and strong SystemVerilog/Verilog expertise.

You will own micro-architecture definitions, develop RTL for complex digital blocks, and coordinate IP integration while supporting sign-off activities (CDC, RDC, lint, synthesis). Collaboration with DV teams is essential.