RTL Designer Engineer

Experis; San Francisco (CA); Remote; USD 83,000 - 118,000; Full time

Job summary

Experis (Austria) seeks an RTL Designer Engineer for a 6-month remote engagement in San Francisco, CA. The role requires 8–15 years of RTL design experience and strong SystemVerilog/Verilog expertise.

You will own micro-architecture definitions, develop RTL for complex digital blocks, and coordinate IP integration while supporting sign-off activities (CDC, RDC, lint, synthesis). Collaboration with DV teams is essential.

Qualifications

• 8-15 years of RTL design experience
• Strong SystemVerilog/Verilog expertise
• Experience defining micro-architecture independently
• Familiarity with sign-off flows including CDC and RDC
• Ability to operate with minimal supervision

Responsibilities

• Own micro-architecture definition from high-level functional specifications
• Develop and implement RTL for complex digital blocks
• Drive digital block control and IP integration
• Participate in subsystem-level architecture alignment
• Support design sign-off activities (CDC, RDC, lint, synthesis readiness)
• Collaborate closely with DV for closure and debug

Skills

RTL design

SystemVerilog/Verilog

IP integration

Memory subsystems

Education

MS in CS or EE

Tools

CDC tooling

Lint/synthesis tooling

Job description

Job Title: RTL Designer Engineer

Location: San Francisco, CA (Remote)

Duration: 6 Months

Pay Rate: $ 73/hr on W2

Job Description

Remote? In office? Hybrid?: Remote

Resource needs to be local?: No

Visa restrictions? : No

Travel and expenses paid by client?: with prior approval

Must-Have skills for the role: see below

Nice-to-have skills: See below

Years of experience needed: 8-15 years

Key Responsibilities

• Own micro-architecture definition from high-level functional specifications
• Develop and implement RTL for complex digital blocks
• Drive digital block control and IP integration
• Participate in subsystem-level architecture alignment
• Support design sign-off activities (CDC, RDC, lint, synthesis readiness)
• Collaborate closely with DV for closure and debug

Required Qualifications

• Strong expertise in RTL design (SystemVerilog/Verilog)
• Experience defining micro-architecture independently
• Solid understanding of memory controllers and digital subsystems
• Experience with IP integration and block-level ownership
• Familiarity with sign-off flows including:
• CDC (Clock Domain Crossing)
• RDC (Reset Domain Crossing)
• Ability to operate with minimal supervision

Preferred

• Experience in subsystem-level development
• Exposure to D2D logic
• Prior experience working directly with major hyperscaler silicon teams

Industry experience needed?: Silicon Engineering

Education needed for the role: MS computer science or Electrical Engineering

Chances of extension?: Yes