RTL Designer Engineer

Experis AB; San Francisco (CA); A distancia; USD 83.000 - 118.000; A tiempo parcial

Descripción de la vacante

Experis Technology Group in San Francisco, CA seeks an experienced RTL Designer Engineer for a remote 6-month engagement. You will own micro-architecture definitions, and develop RTL for complex digital blocks, working with DV teams to close issues.

The role requires deep SystemVerilog/Verilog RTL expertise, independent micro-architecture definition, and strong memory controller knowledge. Prior IP integration experience and sign-off flow familiarity are essential.

Formación

• Must have strong RTL design expertise in SystemVerilog/Verilog.
• Ability to define micro-architecture independently from high-level specs.
• Solid understanding of memory controllers and digital subsystems.
• Experience with IP integration and block-level ownership.
• Familiarity with sign-off flows including CDC and RDC.
• Ability to operate with minimal supervision.

Responsabilidades

• Own micro-architecture definition from high-level functional specifications.
• Develop and implement RTL for complex digital blocks.
• Drive digital block control and IP integration.
• Participate in subsystem-level architecture alignment.
• Support design sign-off activities (CDC, RDC, lint, synthesis readiness).
• Collaborate closely with DV for closure and debug.

Conocimientos

RTL design

SystemVerilog/Verilog

Micro-architecture

Memory controllers

IP integration

CDC/RDC sign-off

Educación

MS in Computer Science or EE

Descripción del empleo

Job Title: RTL Designer Engineer

Location: San Francisco, CA (Remote)

Duration: 6 Months

Pay Rate: $ 73/hr on W2

Job Description: Remote? In office? Hybrid?: Remote Resource needs to be local?: No Visa restrictions? : No Travel and expenses paid by client?: with prior approval Must-Have skills for the role: see below Nice-to-have skills: See below Years of experience needed: 8-15 years

Key Responsibilities

• Own micro-architecture definition from high-level functional specifications
• Develop and implement RTL for complex digital blocks
• Drive digital block control and IP integration
• Participate in subsystem-level architecture alignment
• Support design sign-off activities (CDC, RDC, lint, synthesis readiness)
• Collaborate closely with DV for closure and debug

Required Qualifications

• Strong expertise in RTL design (SystemVerilog/Verilog)
• Experience defining micro-architecture independently
• Solid understanding of memory controllers and digital subsystems
• Experience with IP integration and block-level ownership
• Familiarity with sign-off flows including:
  • CDC (Clock Domain Crossing)
  • RDC (Reset Domain Crossing)
• Ability to operate with minimal supervision

Preferred

• Experience in subsystem-level development
• Exposure to D2D logic
• Prior experience working directly with major hyperscaler silicon teams

Industry experience needed?: Silicon Engineering Education needed for the role: MS computer science or Electrical Engineering Chances of extension?: Yes