Senior RISCV CPU Architect & RTL Engineer

Qualcomm; Santa Clara (CA); On-site; USD 209,000 - 314,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking highly skilled engineers for RISCV CPU RTL development and architecture definition.

You will contribute to microarchitecture, RTL execution of CPU system features, and work on configuration access, timer/interrupt architectures, and power management. The role requires a Master’s degree with extensive CPU RTL experience, deep microarchitectural knowledge, and expertise in Verilog/VHDL, debugging, and waveform analysis.

Qualifications

• Masters degree plus 10+ years in CPU RTL or related field
• Deep knowledge of microprocessor architecture with RISCV, timer/interrupt, configuration access, RAS and safety
• Strong power management expertise for high‑performance systems
• Proven experience in defining and developing debug features for high‑performance designs
• Excellent technical documentation and communication skills

Responsibilities

• Own or contribute to performance and power optimization with CPU modeling team
• Develop high-level architecture and microarchitecture specs translating to RTL
• Own RTL development and refine RTL to meet power, performance, area, timing goals
• Support functional verification and verification strategies
• Deliver design collaboration with cross-functional teams to validate timing, area, reliability and power
• Work with software/firmware/platform teams to enable CPU system features in products

Skills

Verilog

VHDL

RISCV ISA familiarity

Power management

Debug/trace

RTL design fundamentals

Education

Bachelor's degree in Electrical/Computer/CS

Master's degree in Electrical/Computer/CS

PhD in Electrical/CS/Engineering

Job description

Qualcomm Technologies, Inc. is seeking highly skilled engineers for RISCV CPU RTL development and architecture definition.

You will contribute to microarchitecture, RTL execution of CPU system features, and work on configuration access, timer/interrupt architectures, and power management. The role requires a Master’s degree with extensive CPU RTL experience, deep microarchitectural knowledge, and expertise in Verilog/VHDL, debugging, and waveform analysis.