Senior Remote High-Speed Analog Layout Architect

Celero Communications, Inc.; San Jose (CA); Remote; USD 180,000 - 230,000; Full time

Benefits offered by this job

Foundational role

Cross-functional teams

International culture

Grow with Celero

AI/data center connectivity

Job summary

Celero Communication Inc. is a fast-growing semiconductor startup hiring a Senior to Principal High-Speed Analog Layout Engineer in a remote-capable role.

You will drive complex analog/mixed-signal layouts and mentor engineers across time zones, interfacing with CAD/PDK teams to ensure first-pass silicon success. Role emphasizes collaboration with circuit designers, floor planning, power grid implementation, and robust verification using LVS/DRC and industry tools.

Qualifications

• 10+ years of hands-on analog/mixed-signal layout experience in advanced CMOS/FinFET tech.
• Proven IP layout macro ownership or full-chip layout at FinFET nodes (TSMC preferred).
• Experience with TSMC FinFET nodes (N3/N5/N7/N16) and LVS/DRC/PEC checks.

Responsibilities

• Lead physical layout design of complex analog/mixed-signal macros from floor planning to verification.
• Collaborate with schematic designers to optimize layout performance, matching, symmetry and reliability.
• Mentor junior engineers across time zones and enforce layout best practices.
• Perform and debug LVS, DRC, PERC, ERC and other checks with Pegasus, Calibre, etc.
• Contribute to chip-level planning, floor planning, power/grid design, and routing.
• Lead layout reviews and provide technical leadership for quality and schedules.
• Support automation via scripting (SKILL, TCL, Python).

Skills

Analog layout

Mixed-signal design

Leadership

Mentoring

International collaboration

Documentation

Tools

Cadence Virtuoso

Calibre

Pegasus

SKILL

TCL

Python

Job description

Celero Communication Inc. is a fast-growing semiconductor startup hiring a Senior to Principal High-Speed Analog Layout Engineer in a remote-capable role.

You will drive complex analog/mixed-signal layouts and mentor engineers across time zones, interfacing with CAD/PDK teams to ensure first-pass silicon success. Role emphasizes collaboration with circuit designers, floor planning, power grid implementation, and robust verification using LVS/DRC and industry tools.