Lead High-Speed Analog IP Layout Architect

Celero Communications; San Jose (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications is seeking a Senior/Principal Analog Layout Engineer to drive the layout design of complex analog and mixed-signal IP blocks in our advanced optical communication systems. You will lead layout development of ADCs, DACs, PLLs, and other high-performance circuits, interfacing with circuit designers, CAD/PDK teams, and fellow layout engineers to ensure first-pass silicon success.

You will mentor junior engineers across time zones and contribute to chip-level planning,

Qualifications

• 10+ years of hands-on analog/mixed-signal layout experience.
• Experience with FinFET CMOS nodes (TSMC preferred).
• Strong proficiency with LVS/DRC/PERC and signoff checks.

Responsibilities

• Lead physical layout of analog/mixed-signal macros from floor planning to verification.
• Collaborate with schematic designers for optimal layouts.
• Mentor junior layout engineers and contractors across time zones.
• Perform LVS, DRC, PERC, ERC and other signoff checks.
• Contribute to chip-level planning including floor planning and power grid design.
• Lead layout design reviews and ensure quality and schedule adherence.
• Support automation via SKILL, TCL, Python.

Skills

Analog layout

Leadership

Mentoring

Python scripting

Team collaboration

Tools

Cadence Virtuoso

Calibre

Pegasus

Layout verification tools

Job description

Celero Communications is seeking a Senior/Principal Analog Layout Engineer to drive the layout design of complex analog and mixed-signal IP blocks in our advanced optical communication systems. You will lead layout development of ADCs, DACs, PLLs, and other high-performance circuits, interfacing with circuit designers, CAD/PDK teams, and fellow layout engineers to ensure first-pass silicon success.

You will mentor junior engineers across time zones and contribute to chip-level planning,