Lead Analog Layout Architect for High-Speed IP

Celero Communications; Irvine (CA); On-site; USD 150,000 - 250,000; Full time

Benefits offered by this job

High-growth startup

International team

Career growth

AI/Data center focus

Job summary

Celero Communications seeks a Senior/Principal Analog Layout Engineer in Irvine, CA to drive layout development for analog/mixed-signal IP blocks such as ADCs, DACs, and PLLs within a fast-paced AMS design team.

You will interface with circuit designers, CAD/PDK teams, and other layout engineers to ensure first-pass silicon success while mentoring others and contributing to chip development.

Qualifications

• 10+ years of analog/mixed-signal layout experience in advanced CMOS/FinFET technologies.
• Experience leading IP/layout macros or full-chip layouts at FinFET nodes (TSMC preferred).
• Mentor junior/layout engineers and coordinate with cross-functional teams.

Responsibilities

• Lead physical layout of analog/mixed-signal macros from floor planning to final verification.
• Collaborate with schematic designers to optimize layout performance, matching and reliability.
• Mentor junior engineers and contractors across time zones; enforce best practices in layout and verification.

Skills

Hands-on analog/mixed-signal layout

Leadership & mentoring

IP/layout macro ownership

Documentation & communication

Layout verification & signaling

Collaboration across time zones

Tools

Cadence Virtuoso

Calibre

Pegasus

LVS/DRC/PERC/EC

Job description

Celero Communications seeks a Senior/Principal Analog Layout Engineer in Irvine, CA to drive layout development for analog/mixed-signal IP blocks such as ADCs, DACs, and PLLs within a fast-paced AMS design team.

You will interface with circuit designers, CAD/PDK teams, and other layout engineers to ensure first-pass silicon success while mentoring others and contributing to chip development.