Senior IC Verification Engineer – AR Display (UVM/SystemVerilog)

Snap; Washington; Hybrid; USD 147,000 - 259,000; Full time

Benefits offered by this job

RSUs equity

Job summary

Snap Inc. is seeking an Integrated Circuit Design Verification Engineer to join the Spectacles Team to verify AR display ICs alongside digital, analog, software, and verification engineers.

You will develop UVM-based testbenches, create verification plans, and use Siemens Questa tools. Candidates should have a strong SystemVerilog background, RTL experience, and familiarity with video/display protocols.

Qualifications

• BSEE or MSEE or relevant years of experience.
• 10+ years of experience in ASIC Design Verification.
• Strong knowledge of UVM and SystemVerilog for verification.
• Experience with Siemens Questa toolset.
• Experience in RTL design and familiarity with video/display protocols (MIPI/AMBA/I2C/SPI).

Responsibilities

• Work as part of a multi‑disciplinary team designing display ICs for AR.
• Collaborate with digital, analog, software and verification engineers.
• Develop and implement UVM‑based and assertion‑based testbenches.
• Create verification test plans with coverage and code coverage.
• Utilize Siemens Questa tool set for verification and debugging tasks.

Skills

UVM

SystemVerilog

Verilog RTL coding

Scripting (Python)

English communication

Education

BSEE or MSEE

Tools

Siemens Questa

UVM Framework

Job description

Snap Inc. is seeking an Integrated Circuit Design Verification Engineer to join the Spectacles Team to verify AR display ICs alongside digital, analog, software, and verification engineers.

You will develop UVM-based testbenches, create verification plans, and use Siemens Questa tools. Candidates should have a strong SystemVerilog background, RTL experience, and familiarity with video/display protocols.