Senior/Principal Physical Design Engineer: SoC Lead

SKHMS Corporation; San Jose, Northern (CA, KY); Hybrid; USD 160,000 - 220,000; Full time

Job summary

SK hynix memory solutions America Inc. is seeking a Sr. Staff/Principal Physical Design Engineer to drive advanced-node ASIC implementation from RTL to GDS.

You will lead synthesis, placement, CTS, routing, and signoff for high-performance blocks and mentor junior engineers in a fast-moving team. The role requires hands-on expertise across the full physical design flow, collaboration with front-end, DFT, power, and analog teams, and a track record of tapeouts.

Qualifications

• 8+ years of ASIC physical design with tapeout experience.
• Expertise with synthesis, placement, CTS, routing and signoff.
• Strong knowledge of STA and multi-corner/multi-mode closure.

Responsibilities

• Lead physical design implementation from RTL to GDS for high-performance blocks and SoC designs.
• Drive timing closure, signoff, and PPA optimization across advanced nodes (7nm/5nm/3nm).
• Collaborate with front-end, DFT, power and analog teams to ensure silicon success.
• Mentor junior engineers and define team methodologies and flows.
• Manage tapeout schedules and maintain automation scripts (Tcl, Perl, Python).

Skills

Leadership

Mentoring

Team collaboration

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field

Master's preferred

Tools

Synopsys ICC2

Fusion Compiler

Cadence Innovus

PrimeTime

Calibre

StarRC

Quantus

RedHawk

Job description

SK hynix memory solutions America Inc. is seeking a Sr. Staff/Principal Physical Design Engineer to drive advanced-node ASIC implementation from RTL to GDS.

You will lead synthesis, placement, CTS, routing, and signoff for high-performance blocks and mentor junior engineers in a fast-moving team. The role requires hands-on expertise across the full physical design flow, collaboration with front-end, DFT, power, and analog teams, and a track record of tapeouts.