SoC Physical Design Engineer, Senior Member of Technical Staff (SMTS)

Micron Technology, Inc; Folsom (CA); On-site; USD 130,000 - 170,000; Full time

Job summary

Micron Technology, Inc in Folsom, California, is looking for a Senior SoC Physical Design Engineer to drive advanced HBM SoC logic designs from netlist to GDSII. The role involves hands-on responsibilities for SoC blocks integration, ensuring designs meet PPA targets and collaborating across teams.

The ideal candidate will have extensive experience in SoC physical design, proficiency in EDA tools, and strong automation skills. A Bachelor’s or Master’s in Electrical Engineering is preferred along with significant experience in the field.

Qualifications

• Strong experience in SoC physical design implementation from netlist to GDSII.
• Proficiency with industry EDA tools.
• Strong scripting/automation skills.

Responsibilities

• Own physical implementation for SoC blocks including floor planning and placement.
• Drive timing closure across multi-mode scenarios.
• Collaborate with design and integration teams.
• Perform physical signoff including DRC/LVS and timing signoff.

Skills

SoC physical design implementation

EDA tools (Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime)

Scripting/automation (Python, TCL, Perl, Shell)

Education

Bachelor's or Master's degree in Electrical Engineering or related field

Tools

Cadence Innovus

Synopsys ICC2

Siemens Calibre

Job description

SoC Physical Design Engineer, Senior Member of Technical Staff (SMTS)

Req ID: JR103203

In the Heterogeneous Integration Group (HIG), the engineer drives the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. The role works closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA and robust signoff collateral for tapeout. It is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations.

Key Responsibilities

• Own physical implementation for SoC blocks and/or top‑level, including floor planning, placement, CTS, routing, and physical optimization to meet PPA targets.
• Drive timing closure (setup/hold) across multi‑mode/multi‑corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs.
• Collaborate with design and integration teams to ensure clean implementation of clocking/reset strategy, power architecture, and SoC integration requirements.
• Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity.
• Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently.
• Work with packaging, assembly, test, probe, and manufacturing stakeholders to ensure design meets manufacturability and quality requirements.
• Support tapeout execution (checklists, ECO flows, signoff reviews) and contribute to post‑silicon debug by correlating silicon behavior with PD/STA/power analysis.
• Identify flow gaps and improve productivity through scripting/automation and best‑practice methodology development.

Required Qualifications

• Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs.
• Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent).
• Experience with power intent and power delivery considerations (e.g., UPF/CPF concepts, power grid planning, power gating implications).
• Exposure to hierarchical physical design, top‑level assembly, partitioning guidelines, and large‑scale integration methodology.
• Knowledge of IR/EM analysis, noise, coupling/crosstalk considerations, and mitigation strategies.
• Proven tapeout history on advanced foundries (e.g., TSMC) and understanding of full‑cycle SoC development flows.
• Strong scripting/automation skills using Python, TCL, Perl, and/or shell.

Preferred Qualifications

• Experience with HBM / DRAM adjacent SoC designs, or memory‑subsystem‑heavy SoCs.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum 15 years of experience in a related field.

Job Profile(s)

Systems Design Engineering MTS - Systems Design Engineering SMTS