Principal Layout Designer, Next-generation HBM Architecture

Micron Technology, Inc; Richardson (TX); On-site; USD 100,564 - 168,067; Full time

Job summary

Micron Technology, Inc. is seeking a Principal Layout Designer for next‑generation HBM architecture.

You will drive analog and mixed‑signal layout for 3D‑stacked memories, collaborating with architecture, design and packaging teams to prove feasibility and identify optimizations. Responsibilities include layout for critical blocks, floorplanning, placement and routing, LVS/DRC verification, and thorough documentation.

Qualifications

• Hands-on layout experience with analog blocks and full designs.
• Strong understanding of analog layout fundamentals and parasitics.
• Experience with LVS/DRC verification and layout quality checks.

Responsibilities

• Design layouts for critical analog and mixed-signal blocks.
• Lead layout exploration: floorplanning, placement, routing.
• Integrate full chip designs and perform LVS/DRC with documentation.
• Collaborate across domains (SI, architecture, packaging) for exploration.

Skills

Analog layout

Mixed-signal layout

LVS/DRC verification

Parasitics understanding

Education

Bachelor’s or Master’s in EE/CE/CS

Tools

Cadence VLE/VXL

Mentor Calibre DRC/LVS

Job description

Principal Layout Designer, Next‑generation HBM Architecture

As a Principal Layout Designer in Micron’s High Bandwidth Memory Architecture organization, you will drive layout for 3D‑stacked, high‑performance memories. You will apply your knowledge to deliver high‑quality layout designs across analog and/or mixed‑signal domains in collaboration with peer architecture, design, and packaging teams, and implement layout designs for early architecture concepts to demonstrate feasibility and identify optimizations.

Responsibilities

• Design layouts for critical analog and mixed‑signal blocks.
• Drive exploratory layout process for next‑generation architectures, including floorplanning, placement, and routing.
• Integrate full chip designs and perform layout verification (LVS, DRC), quality checks, and documentation.
• Collaborate and communicate across domains, including signal integrity, architecture, design, and advanced packaging, to ensure successful architecture exploration.

Minimum Qualifications

• Hands‑on layout experience with critical analog blocks and full designs.
• Experience with Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS.
• Solid understanding of layout impacts: speed, capacitance, power, and area.
• Strong understanding of analog layout fundamentals: matching, electro migration, latch‑up, coupling, crosstalk, IR‑drop, and parasitic effects.

Preferred Qualifications

• Demonstrated layout ability for DRAM designs.
• Excellent communication, collaboration, and problem‑solving skills.
• 8+ years of experience in analog and/or mixed‑signal layout designs.
• Bachelor’s or Master’s degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent experience.

Job Profiles

Layout/Mask Designer E4 – Layout/Mask Designer E5

Relocation Level

TBD

Compensation

US base salary range: $62.25 – $122.00 an hour. Additional compensation may include benefits, bonuses and equity. The paid time‑off program, paid holidays, and various benefit plans (medical, dental, vision, income protection, family leave) are provided. Compensation details reflect the base salary only and do not include bonus, equity, or benefits.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.