Senior Principal Digital IC Design Engineer (Equity)

Cadence; San Jose (CA); On-site; USD 161,000 - 299,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Cadence seeks an energetic Senior Pre-sales Engineer for Digital IC at our California design center. You will support customers, drive pre- and post-sales activities for Cadence Digital IC tools.

Responsibilities include enabling customers on Place & Route flows, conducting demonstrations and benchmarks, and collaborating with R&D to improve flows while mentoring junior engineers. Competitive salary and benefits offered.

Qualifications

• Requires a BS, MS, or PhD in EE with 10–12 years in digital implementation/EDA.
• Deep understanding of ASIC design flow from RTL to GDS.
• Hands-on with Place & Route and synthesis tools as listed.
• Experience with STA/SDC debugging and power/clock analysis.
• Strong customer-facing communication and presentation skills.

Responsibilities

• Provide technical support to customers in Digital Design Implementation & Signoff.
• Guide customers on how to utilize Cadence tools to meet goals.
• Conduct technical presentations and product demonstrations.
• Drive evaluations/benchmarks to success.
• Collaborate with R&D to enhance tools and methodologies.
• Drive adoption of Cadence tools and technologies.
• Augment flows using Tcl and other scripting.
• Capture best practices from evaluations to improve next engagements.
• Provide technical support when developing business cases.
• Mentor junior engineers.

Skills

Place & Route

Scripting (Perl/Tcl/Shell)

Customer interaction

Analytical thinking

Education

BS/MS/PhD in EE

Tools

Innovus

ICC2

Fusion Compiler

Genus

RTL Compiler

Design Compiler

Job description

Cadence seeks an energetic Senior Pre-sales Engineer for Digital IC at our California design center. You will support customers, drive pre- and post-sales activities for Cadence Digital IC tools.

Responsibilities include enabling customers on Place & Route flows, conducting demonstrations and benchmarks, and collaborating with R&D to improve flows while mentoring junior engineers. Competitive salary and benefits offered.