Senior Principal Design Engineer

Cadence; San Jose (CA); On-site; USD 154,000 - 286,000; Full time

Job summary

Join an innovative engineering team at a leading technology firm, where you will play a crucial role in developing cutting-edge ASIC designs. This position offers the opportunity to work on the industry-leading Palladium Emulation system, utilizing the latest technology and methodologies. You will be responsible for ensuring timing closure and collaborating with cross-functional teams to drive improvements. If you are a motivated problem solver with extensive ASIC design experience, this is an exciting opportunity to make a significant impact in the tech world.

Benefits

Paid vacation

401(k) plan with employer match

Employee stock purchase plan

Medical, dental, and vision plan options

Qualifications

• 10+ years of ASIC Design experience required.
• Strong understanding of SOC design and flow.
• Experience with large design STA and Timing Closure.

Responsibilities

• Develop and debug design constraints across various hierarchies.
• Collaborate with design teams to facilitate logic changes.
• Implement timing infrastructure and maintain scripts for analysis.

Skills

ASIC Design

STA methodologies

scripting languages (PERL, Python, Tk/TCL, Shell)

problem-solving skills

communication skills

Education

BS in Electrical or Computer Engineering

MS in Electrical or Computer Engineering

PhD in Electrical or Computer Engineering

Job description

Join to apply for the Senior Principal Design Engineer role at Cadence

2 weeks ago Be among the first 25 applicants

Join to apply for the Senior Principal Design Engineer role at Cadence

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are a great and passionate engineering team building the next Palladium Emulation ASIC and system at Cadence Design System.

Palladium has been the leader in the industry over the past 20 years and we are pushing the envelope using the latest technology node and methodologies.

Palladium is a massively parallel system with 1000s of custom processors tightly interconnected together through a custom and proprietary mesh using the latest tools and IPs from Cadence.

Key Responsibilities

• Will be responsible for developing and debugging design constraints across all modes and level of hierarchies (block / subChip / top)
• The candidate will routinely discuss with Design team to facilitate logic changes and improved / drive timing to closure.
• The position will interact with both Front End (Design / DFT) and Back End Implementation Teams (P&R).
• Proficient in STA and methodologies for timing closure, and have a good understanding of noise, cross-talk, and OCV effects, among others.
• Experience with large design STA and Timing Closure.
• Familiar with ECO techniques and implementation.
• Maintain scripts and methodologies for analysis and runs.
• Implement timing infrastructure.
  
  

Requirements

• BS in electrical or computer engineering with a minimum of 10 years of ASIC Design experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience
• Excellent written and verbal communication skills.
• Understanding of complete SOC design and flow.
  
  

Desired

• Self-motivated team player with strong problem-solving and analytical skills to collaborate with various teams to achieve desired goals
• Experience in at least one scripting language like PERL, Python, Tk/TCL or Shell is preferred.
  
  

The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Job function

  Engineering and Information Technology

• Industries

  Software Development

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