Senior Principal Design Engineer - DFT

Cadence; San Jose (CA); On-site; USD 154,000 - 286,000; Full time

Job summary

An innovative firm is seeking a Senior Principal Design Engineer specializing in DFT for next-generation SoCs. This role involves defining DFT architecture, collaborating with cross-functional teams, and ensuring effective implementation and verification of DFT logic. The company promotes a culture of creativity and teamwork, offering opportunities for professional growth and development. With a focus on cutting-edge technology, this position is perfect for those looking to make a significant impact in the tech industry. Join a diverse and passionate team dedicated to excellence and innovation.

Benefits

Paid vacation

401(k) with employer match

Stock purchase plans

Medical/dental/vision coverage

Qualifications

• 10+ years of experience in DFT or equivalent education.
• Hands-on experience with scan, PMBIST, and JTAG.

Responsibilities

• Define DFT architecture for next-gen SoCs and implement verification.
• Collaborate with teams for DFT structure development and verification.

Skills

DFT concepts

Scan compression

Verilog

Scripting languages (Perl, Python, TCL, Shell)

Problem-solving skills

Strong communication abilities

Education

BS in Electrical Engineering

MS in Electrical Engineering

PhD in Electrical Engineering

Tools

EDA tools

Job description

Join to apply for the Senior Principal Design Engineer - DFT role at Cadence.

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The Cadence Advantage

Cadence offers the opportunity to work on cutting-edge technology in an environment that encourages creativity, innovation, and impact. Our employee-friendly policies focus on physical and mental well-being, career development, learning opportunities, and celebrating success. The "One Cadence – One Team" culture promotes collaboration to ensure customer success. We provide multiple avenues for learning and development tailored to employees' interests. Join a diverse team of passionate, dedicated, and talented individuals committed to excellence daily.

Key Responsibilities

The Senior Principal Design Engineer will define the DFT architecture for next-generation SoCs, including implementation and verification of scan, PMBIST, JTAG, and other DFT logic. Responsibilities also include developing DFT insertion methodologies, pattern development, manufacturing tests, and verifications. The role involves close collaboration with cross-functional teams to develop and verify DFT structures and constraints, RTL and gate-level simulations, and working with Test Engineering for test program development, silicon bring-up, diagnosis, and yield improvement. Additionally, working with EDA RnD teams to propose and implement new features is expected.

Requirements

• BS in Electrical Engineering, Computer Engineering, or Computer Science with 10+ years of experience, or MS with 7+ years, or PhD with 5+ years.
• At least 8 years of hands-on experience in DFT.
• Strong understanding of DFT concepts like Scan compression, fault models, IEEE standards (P1500, 1149.1/6, 1687), MBIST.
• Proficiency in RTL coding (Verilog), Synthesis & STA.
• Experience with scripting languages (Perl, Python, TCL, Shell) preferred.
• Self-motivated team player with problem-solving skills and strong communication abilities.

The annual salary range for California is $154,000 to $286,000, with potential incentives including bonuses, equity, and benefits. Compensation varies based on qualifications, skills, and location. Benefits include paid vacation, holidays, 401(k) with employer match, stock purchase plans, medical/dental/vision coverage, and more.

We’re doing work that matters. Help us solve what others can’t.

Seniority level

• Not Applicable

Employment type

• Full-time

Job function

• Engineering and Information Technology

Industries

• Software Development