Senior Principal Design Engineer - DFT

Cadence Design Systems; San Jose (CA); On-site; USD 154,000 - 286,000; Full time

Job summary

Join an innovative company as a Senior Principal Design Engineer, where you'll define and implement cutting-edge DFT architectures for next-generation SoCs. This role involves working closely with cross-functional teams to ensure successful verification and testing of DFT structures. You will leverage your extensive experience in DFT concepts and RTL coding to drive impactful projects. The company fosters a collaborative environment, encouraging creativity and personal growth, making it an exciting opportunity for those passionate about technology and innovation. If you're ready to make a difference and tackle challenges in the tech world, this position is for you.

Benefits

Paid vacation

401(k) plan with employer match

Employee stock purchase plan

Medical, dental, and vision plan options

Qualifications

• 10+ years experience in DFT with strong knowledge of key concepts.
• Proficient in Verilog and at least one scripting language.

Responsibilities

• Define DFT Architecture for next generation SoCs and implement verification.
• Collaborate with teams for DFT structures and perform simulations.

Skills

Design for Test (DFT)

Verilog

Scan compression

Scripting (PERL, Python, TCL, Shell)

Problem-solving

Communication skills

Education

BS in Electrical Engineering, Computer Engineering or Computer Science

MS in related field

PhD in related field

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The Cadence Advantage

Cadence offers the opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success. Multiple avenues of learning and development are available for employees to explore as per their specific requirements and interests. Additionally, you get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

Key Responsibilities

The Senior Principal Design Engineer will define the DFT Architecture for the next generation SoCs. This person will also be responsible for the implementation & verification including Scan, PMBIST, JTAG and other DFT-related logic. Additionally, they will define and develop methodology for DFT insertion, pattern development, manufacturing tests, verifications, etc. They will work closely with cross-functional teams to develop and verify DFT structures and constraints as well as perform RTL and gate level (no-timing and timing) simulations to verify DFT functionality. Finally, they will work closely with Test Engineering for test program development and Silicon bring up, diagnosis, Yield improvement, etc. and work closely with EDA RnD teams to propose and implement new features.

Requirements:

• BS in Electrical Engineering, Computer Engineering or Computer Science with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience
• At least 8 years of relevant hands-on experience in Design for Test (DFT).
• Clear understanding of key DFT concepts like Scan compression, Scan Stitching, fault models (stuck-at, delay tests, IDDQ, Small Delay, etc.), IEEE P1500, MBIST, IEEE 1149.1/6 (Boundary scan), IEEE 1687, etc.
• Working knowledge of RTL coding in Verilog, Synthesis & STA
• Experience in at least one scripting language like PERL, Python, TCL, or Shell is preferred.
• Self-motivated team player with strong problem-solving skills to collaborate with various teams to achieve desired goals.
• Excellent written and verbal communication skills.

The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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