Senior Principal Design Engineer

Cadence Design Systems; San Jose (CA); On-site; USD 154,000 - 286,000; Full time

Job summary

An established industry player is seeking a seasoned ASIC Design Engineer to join their innovative team. This role involves developing and debugging design constraints, collaborating with cross-functional teams, and utilizing advanced methodologies for timing closure. With a commitment to pushing the boundaries of technology, the company offers a dynamic environment where your expertise will contribute to groundbreaking advancements. If you are a motivated problem-solver with a passion for technology, this opportunity is perfect for you to make a significant impact in the field.

Benefits

Paid vacation

Paid holidays

401(k) plan with employer match

Employee stock purchase plan

Medical, dental, and vision plan options

Qualifications

• 10+ years of ASIC Design experience or equivalent education and experience.
• Strong understanding of SOC design and flow.

Responsibilities

• Develop and debug design constraints across all hierarchy levels.
• Collaborate with Design team to improve timing closure.

Skills

ASIC Design

STA methodologies

Scripting (PERL, Python, Tk/TCL, Shell)

Communication Skills

Problem-solving

Education

BS in Electrical or Computer Engineering

MS in Electrical or Computer Engineering

PhD in Electrical or Computer Engineering

Tools

Custom processors

Timing infrastructure tools

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are a great and passionate engineering team building the next Palladium Emulation ASIC and system at Cadence Design System.

Palladium has been the leader in the industry over the past 20 years and we are pushing the envelope using the latest technology node and methodologies.

Palladium is a massively parallel system with 1000s of custom processors tightly interconnected together through a custom and proprietary mesh using the latest tools and IPs from Cadence.

Key Responsibilities

1. Will be responsible for developing and debugging design constraints across all modes and levels of hierarchies (block / subChip / top).
2. The candidate will routinely discuss with the Design team to facilitate logic changes and improve/drive timing to closure.
3. The position will interact with both Front End (Design / DFT) and Back End Implementation Teams (P&R).
4. Proficient in STA and methodologies for timing closure, and have a good understanding of noise, cross-talk, and OCV effects, among others.
5. Experience with large design STA and Timing Closure.
6. Familiar with ECO techniques and implementation.
7. Maintain scripts and methodologies for analysis and runs.
8. Implement timing infrastructure.

Requirements :

1. BS in electrical or computer engineering with a minimum of 10 years of ASIC Design experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience.
2. Excellent written and verbal communication skills.
3. Understanding of complete SOC design and flow.

Desired

1. Self-motivated team player with strong problem-solving and analytical skills to collaborate with various teams to achieve desired goals.
2. Experience in at least one scripting language like PERL, Python, Tk/TCL or Shell is preferred.

The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies, and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental, and vision plan options, and more.

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