Senior Principal CMOS Device Design Architect - Hybrid

Intel Corporation; Hillsboro (OR); Hybrid; USD 265,000 - 375,000; Full time

Job summary

Intel Corporation in Hillsboro, Oregon, seeks a Senior Principal Device Design Engineer to lead high-level architecture and optimization of next-gen semiconductor technologies for high-volume manufacturing. You will bridge Process Integration, Yield, and Module Eng.

with product partners to define directions and validate silicon feasibility. Required expertise includes CMOS device physics, cross-functional leadership, and DOE/data analytics to drive design decisions and ensure world-class

Qualifications

• Progressive experience in the semiconductor industry with a strong focus on CMOS device physics, device design, and semiconductor technology development.
• Leadership within the semiconductor industry, leading cross-functional teams to define, develop, and deliver advanced technologies for HVM.
• Design rule governance with understanding of how layout constraints impact product yield.
• Data analysis and DOE experience to evaluate test chips, E-test, and yield trends.

Responsibilities

• Lead cross-functional, multi-disciplinary teams in defining base and derivative semiconductor architectures for high-performance logic, memory, and mixed-signal apps.
• Partner with external customers and internal groups to translate product needs into tailored silicon solutions.
• Drive customization and optimization of semiconductor features across logic and memory teknologies for seamless integration.
• Set device and interconnect performance targets and assess silicon-to-simulation health for large-volume manufacturing.
• Coordinate with Process Integration, Yield, Module Eng., and Product Design for technology handoffs.
• Direct validation and waiver governance for design rules to balance yield and design flexibility.
• Evaluate electrical test and yield data using statistics to derive actionable process insights.
• Provide senior mentorship and stay ahead of industry trends to foster technical excellence.

Skills

CMOS device physics

Device design

Semiconductor technology development

Leadership in tech integration

Education

Master's degree in Electrical Engineering, Physics, Material Science, or a related field

Tools

Physical Verification Flows

Mask generation concepts

Statistical Process Control (SPC) tools

Job description

Intel Corporation in Hillsboro, Oregon, seeks a Senior Principal Device Design Engineer to lead high-level architecture and optimization of next-gen semiconductor technologies for high-volume manufacturing. You will bridge Process Integration, Yield, and Module Eng.

with product partners to define directions and validate silicon feasibility. Required expertise includes CMOS device physics, cross-functional leadership, and DOE/data analytics to drive design decisions and ensure world-class