Senior Principal Device Design Engineer — Hybrid Role

Intel Corporation

Hillsboro (OR)

Hybrid

USD 265,000 - 375,000

Full time

3 days ago
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Benefits offered by this job

Stock bonuses
Health benefits
Vacation

Job summary

Intel Corporation in Hillsboro seeks a Senior Principal Device Design Engineer to steer high-volume manufacturing technologies across logic, memory and analog domains. You will lead architecture, engage customers, and harmonize process integration with product needs.

The role demands a PhD or MS with 15+ years in semiconductor device development, strong leadership, and expertise in device physics, design rules, and data analytics. This position offers a hybrid work model.

Qualifications

  • Progressive experience in CMOS device physics, device design, and technology development.
  • Leadership in cross-functional teams to deliver advanced semiconductor technologies.
  • Strong understanding of design rules, verification, and yield impact.

Responsibilities

  • Lead architecture and technical strategy for high-volume manufacturing technologies.
  • Engage with external customers and internal teams to translate requirements into silicon solutions.
  • Guide silicon-to-simulation readiness and bridge process integration with product design.
  • Oversee design rule governance, waiver processes, and data-driven yield analysis.
  • Mentor engineers and drive technical thought leadership in the organization.

Skills

CMOS device physics
Device design
Leadership
DOE & data analysis

Education

Master's degree in Electrical Engineering / Physics / Materials Science
PhD preferred

Tools

DRC tools
SPC software

Job description

Intel Corporation in Hillsboro seeks a Senior Principal Device Design Engineer to steer high-volume manufacturing technologies across logic, memory and analog domains. You will lead architecture, engage customers, and harmonize process integration with product needs.

The role demands a PhD or MS with 15+ years in semiconductor device development, strong leadership, and expertise in device physics, design rules, and data analytics. This position offers a hybrid work model.

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