Senior Principal Analog CAD & EDA Methodology Engineer

Ampere; Durham (NC); On-site; USD 187,000 - 281,000; Full time

Benefits offered by this job

Premium health insurance

Dental and vision insurance

401K retirement plan

Unlimited flextime

Job summary

Ampere is seeking a Senior Principal Analog Methodology Engineer to lead the optimization of analog and mixed‑signal design flows and environments. You will enhance CAD tool workflows, Cadence Virtuoso, and PDK integrations to boost productivity and IP quality.

You will drive automation via SKILL, Python, and Perl, coordinate with foundries for PDK alignment, and supervise large design data and environments to enable fast, reliable tape-outs on cutting‑edge nodes.

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering or equivalent.
• 12+ years of related experience or 8+ years with a Master’s or 5 years with a PhD.
• Strong experience with analog design, layout methodology, and EDA tool support.

Responsibilities

• Define and optimize analog/mixed-signal design flows and environments.
• Integrate and validate PDKs for advanced technology nodes.
• Develop scripts (SKILL, Python, Perl) to automate flows and reduce manual work.
• Collaborate with vendors and internal teams to evaluate new EDA tools.
• Manage Linux compute farms and license servers to sustain design productivity.
• Govern large analog libraries and technology files for scalable IP releases.
• Support design teams to accelerate tape-out schedules with robust verification.

Skills

analog design

layout methodology

EDA tool support

Cadence Virtuoso

Python scripting

shell scripting

foundry PDKs

Education

Bachelor’s degree in Electrical or Computer Engineering

Tools

Cadence tools

Spectre/SPICE simulators

LSF license servers

Job description

Ampere is seeking a Senior Principal Analog Methodology Engineer to lead the optimization of analog and mixed‑signal design flows and environments. You will enhance CAD tool workflows, Cadence Virtuoso, and PDK integrations to boost productivity and IP quality.

You will drive automation via SKILL, Python, and Perl, coordinate with foundries for PDK alignment, and supervise large design data and environments to enable fast, reliable tape-outs on cutting‑edge nodes.