Principal CAD Engineer

Niuro; Santa Clara (CA); Hybrid; USD 150,000 - 210,000; Full time

Job summary

Niuro in Santa Clara, CA is seeking a Principal CAD Engineer to drive the technical direction for CMOS IC CAD flows, including EDA tool suites and PDK customization. This onsite role emphasizes optimization, performance testing, and tapeout support across multiple sites.

You will interface with major EDA vendors, develop automation scripts, and ensure compliance with foundry quality standards to enhance design efficiency.

Qualifications

• Bachelor's degree or higher in Electrical Engineering, Computer Science, or related field.
• Minimum 8 years of CMOS IC CAD support and new product development experience.
• C2 English level or higher.
• Onsite 5 days a week in Santa Clara, CA.

Responsibilities

• Provide full lifecycle support for custom CAD flows across Cadence, Synopsys, Siemens, and Keysight platforms.
• Own PDK installation, validation, customization, maintenance, and release management.
• Support end-to-end tapeout flows and coordinate tapeout submissions to foundries.
• Develop CAD utilities, automation scripts, and regression flows to improve efficiency.
• Interface with EDA vendors to resolve issues and influence product improvements.
• Provide CAD software and Linux user support for CMOS design and IC layout engineers, including documentation.

Job description

The Principal CAD Engineer will drive the technical direction and support for custom CAD flows across Digital, Analog, and Mixed-Signal designs. This role owns the implementation, performance testing, and deployment of new software releases from major EDA vendors, ensuring that multi-site IC design teams have optimized, high-performance environments.In this onsite role, you will take full ownership of PDK installation, customization, and validation, while supporting critical end-to-end tapeout flows. By interfacing directly with EDA vendors and developing custom automation scripts, you will directly improve design efficiency and ensure compliance with foundry quality standards.

Responsibilities

• Provide full lifecycle support for custom CAD flows, including tool development, installation, configuration, maintenance, and upgrades across Cadence, Synopsys, Siemens, and Keysight platforms.
• Own PDK installation, validation, customization, maintenance, and release management to ensure alignment with foundry requirements.
• Support and maintain end-to-end tapeout flows, coordinating and executing tapeout submissions to foundries while ensuring compliance with quality standards.
• Develop and maintain CAD utilities, automation scripts, and regression flows to improve design efficiency and consistency.
• Interface directly with EDA vendors' application and support teams to resolve technical issues and influence product improvements.
• Provide CAD software and Linux user support for CMOS design and IC layout engineers, including preparing user documentation and training materials.

Requirements

• Minimum 8 years of experience in CMOS IC CAD support and new product development.
• C2 English level or higher.
• Ability to work onsite 5 days a week in Santa Clara, CA.
• BA/BS degree in Electrical Engineering, Computer Science, or a related field.
• Proven experience supporting Cadence Virtuoso (Schematic Editor, Layout Suite), Spectre, Innovus, Tempus, Assura, PVS, and Pegasus.
• Proven experience with Siemens Analog Fast-Spice, Questa, and Calibre (PVS, XRC).
• Experience with Synopsys tools, including Design Compiler, VCS, and SpyGlass.
• Proficiency in programming and scripting languages including DFII SKILL, Perl, MATLAB, Tcl/Tk, C/C++, and Python within a Linux environment.
• Hands-on experience with Synopsys Design Compiler, PDK.

Skills

Required

Cadence Virtuoso Spectre Innovus Tempus Assura PVS Pegasus Siemens Analog Fast-Spice Questa Calibre Synopsys Design Compiler VCS SpyGlass DFII SKILL Perl MATLAB Tcl/Tk C++ Python Linux PDK CMOS