Senior Principal Analog Methodology Engineer

Ampere; Durham (NC); On-site; USD 187,000 - 281,000; Full time

Benefits offered by this job

Premium health insurance

Dental and vision insurance

401K retirement plan

Unlimited flextime

Job summary

Ampere is seeking a Senior Principal Analog Methodology Engineer to lead the optimization of analog and mixed‑signal design flows and environments. You will enhance CAD tool workflows, Cadence Virtuoso, and PDK integrations to boost productivity and IP quality.

You will drive automation via SKILL, Python, and Perl, coordinate with foundries for PDK alignment, and supervise large design data and environments to enable fast, reliable tape-outs on cutting‑edge nodes.

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering or equivalent.
• 12+ years of related experience or 8+ years with a Master’s or 5 years with a PhD.
• Strong experience with analog design, layout methodology, and EDA tool support.

Responsibilities

• Define and optimize analog/mixed-signal design flows and environments.
• Integrate and validate PDKs for advanced technology nodes.
• Develop scripts (SKILL, Python, Perl) to automate flows and reduce manual work.
• Collaborate with vendors and internal teams to evaluate new EDA tools.
• Manage Linux compute farms and license servers to sustain design productivity.
• Govern large analog libraries and technology files for scalable IP releases.
• Support design teams to accelerate tape-out schedules with robust verification.

Skills

analog design

layout methodology

EDA tool support

Cadence Virtuoso

Python scripting

shell scripting

foundry PDKs

Education

Bachelor’s degree in Electrical or Computer Engineering

Tools

Cadence tools

Spectre/SPICE simulators

LSF license servers

Job description

Invent the future with us.Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AI compute.

Description

Invent the future with us.

Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AI compute.

As a pioneer in the new frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications.

About The Role

As a Senior Principal Analog Methodology Engineer, you will be a key technical expert responsible for defining and optimizing our analog and mixed-signal design ecosystem. You will focus on enhancing our CAD tool flows, design environments (Cadence Virtuoso), and Process Design Kit (PDK) integrations. Your work will directly enhance design productivity, ensure high-quality IP releases, and enable our design teams to succeed on the most advanced technology nodes.

What You'll Achieve

• Develop, maintain, and automate analog design flows covering schematic capture, simulation, and verification processes including DRC, LVS, PEX, and EM/IR analysis
• Integrate and validate foundry Process Design Kits (PDKs) tailored to specific technology nodes
• Create and maintain scripts (e.g., SKILL, Python, Perl) to improve efficiency, reduce manual tasks, and minimize rework
• Collaborate with vendors and internal teams to evaluate, benchmark, and integrate cutting-edge EDA tools into our existing design ecosystem
• Manage Linux-based design environments, including compute farms (LSF) and license servers
• Oversee design data governance by managing large-scale analog libraries, hierarchical structures, and technology files
• Collaborate closely with analog designers and CAD teams to enhance verification robustness and accelerate tape-out schedules

About You

• Proven experience in analog design and layout methodology, and EDA tool support
• Strong expertise with Cadence Virtuoso/Custom Compiler, SPICE/Spectre simulators, Virtuoso ADE simulation tool suite, and layout verification tools
• High proficiency in scripting with SKILL, shell programming, and Python for automation solutions
• Experience working with foundry PDKs at advanced technology nodes
• Innovative mindset, consistently seeking out and evaluating new methodologies, EDA tools, and emerging technologies (e.g., AI/ML in EDA) to drive efficiency and performance
• Electrical or Computer Engineering - Bachelor’s degree & 12 years of related experience; or Master's degree & 8 years; or PhD & 5 years

What We’ll Offer

At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, cash long-term incentive, and comprehensive benefits. The full base pay range for this role is between $187,000 and $281,000, except in the San Francisco Bay Area where the range is between $204,000 and $306,000.

Our benefits include health, wellness, and financial programs that support employees through every stage of life.

Benefit Highlights Include

• Premium medical insurance, dental insurance, vision insurance, as well as income protection and a 401K retirement plan, so that you can feel secure in your health and financial future.
• Unlimited Flextime and 10+ paid holidays so that you can embrace a healthy work-life balance.
• A variety of healthy snacks, energizing espresso, and refreshing drinks to keep you fueled and focused throughout the day.

And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are excited to share more about our career opportunities with you through the interview process.

Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.