Distinguished CAD Architect — SoC/ASIC, Unlimited Flextime

Ampere; Santa Clara (CA); On-site; USD 280,000 - 420,000; Full time

Benefits offered by this job

Health Insurance

401K plan

Unlimited flextime

Paid holidays

Snacks & beverages

Job summary

Ampere Computing seeks a distinguished engineer to lead the development and optimization of CAD flows for high-performance CPUs/SoCs. You will guide architecture, design, verification, and manufacturing teams to implement cutting-edge CAD strategies that boost productivity and chip performance.

With 15+ years in CAD/EDA, you will shape RTL synthesis, placement and routing, timing closure, and DFM. Expertise in Innovus, Fusion Compiler, PrimeTime, and Calibre is essential.

Qualifications

• 15+ years of experience in semiconductor CAD/EDA development or flow engineering.

Responsibilities

• Define the global physical design methodology across synthesis, floorplanning, placement, CTS, routing, timing closure, and physical verification.
• Architect and deploy advanced CAD flows to support high-performance SoC/ASIC designs.
• Explore AI/ML-driven EDA features to optimize PPA and shorten turnaround times.
• Build and drive PPA optimization recipes for multi-subsystem designs.
• Drive innovation in hierarchical design, multi-die/chiplet integration, and IC design methodologies.
• Develop scripting infrastructure (Tcl, Python, Perl) to automate tasks and ensure flow consistency.

Skills

CAD/EDA leadership

SoC/CPU design

RTL synthesis

Python

Tcl

Perl

Mentoring

Cross-functional collaboration

Education

Electrical or Computer Engineering degree

Tools

Innovus

Fusion Compiler

PrimeTime

Calibre

Job description

Ampere Computing seeks a distinguished engineer to lead the development and optimization of CAD flows for high-performance CPUs/SoCs. You will guide architecture, design, verification, and manufacturing teams to implement cutting-edge CAD strategies that boost productivity and chip performance.

With 15+ years in CAD/EDA, you will shape RTL synthesis, placement and routing, timing closure, and DFM. Expertise in Innovus, Fusion Compiler, PrimeTime, and Calibre is essential.