Senior Power Integrity CAD Methodology Architect

NVIDIA AI; Santa Clara (TX); On-site; USD 240,000 - 350,000; Full time

Job summary

NVIDIA is seeking a Senior Power Integrity Methodology CAD Engineer to advance rail analysis and signoff for its advanced chips. The role emphasizes crafting workflows and innovative solutions across multiple projects, collaborating with hardware and design teams to drive EMIR signoff.

The position requires a Master's in Electrical Engineering (or equivalent), 10+ years in EMIR flow development, and strong scripting with TCL, Perl, Python, and C++.

Qualifications

• Master's degree or equivalent experience in Electrical Engineering or related field.
• 10+ years of experience in EMIR flow methodology development and support.
• Strong understanding of all aspects of EMIR analysis and signoff.
• Familiar with hierarchical design approach and hierarchical signoff.
• Experience with shift-left methodologies for EMIR optimization and convergence earlier in the chip build cycle.
• Ability to collaborate across teams with hardware and design teams to facilitate EMIR signoff.
• Proficiency in programming and scripting languages, such as TCL, Perl, Python, and C++.

Responsibilities

• Developing physical design methodologies for rail analysis and signoff.
• Responsible for coming up with unique and creative solutions for pioneering IR analysis and signoff that are needed for NVIDIA chips.
• Crafting workflows and tool methodologies for power and noise analysis across multiple projects.

Skills

EMIR flow experience

Cross-functional collaboration

Scripting languages

Education

Master's degree in Electrical Engineering

Tools

TCL

Perl

Python

C++

Job description

NVIDIA is seeking a Senior Power Integrity Methodology CAD Engineer to advance rail analysis and signoff for its advanced chips. The role emphasizes crafting workflows and innovative solutions across multiple projects, collaborating with hardware and design teams to drive EMIR signoff.

The position requires a Master's in Electrical Engineering (or equivalent), 10+ years in EMIR flow development, and strong scripting with TCL, Perl, Python, and C++.