Senior DFT Power Methodology Engineer | Equity Options

NVIDIA Corporation; Santa Clara (CA); On-site; USD 196,000 - 368,000; Full time

Benefits offered by this job

Equity compensation

Health benefits

Career growth opportunities

Job summary

NVIDIA in Santa Clara, CA is seeking a Senior DFT Power Methodology Engineer to innovate DFT power, thermal and voltage-noise methodologies, enabling low-power manufacturing tests for datacenter GPUs.

You will collaborate with Product Development & Power Architecture, mentor junior engineers, apply AI/ML solutions to EDA challenges, and perform post-silicon data analysis to shape next‑gen products and test strategies.

Qualifications

• Requires advanced degree and 6+ years (PhD) or 10+ years (MSEE) or 12+ years (BSEE) in DFT design & power.
• Strong understanding of DFT topics and VLSI power/voltage noise.
• Experience with data analysis tools and post-silicon debugging.

Responsibilities

• Innovate DFT power, thermal & voltage-noise methodologies.
• Support low-power manufacturing tests for datacenter GPUs.
• Mentor junior engineers on test designs and trade-offs.

Skills

DFT Methodology

Power Analysis

AI/ML in EDA

RTL/Clocks design

Silicon Debug

Statistical analysis

Education

BSEE/MSEE/PhD

Tools

IR Drop tools

Power tools

ATE platforms

Job description

NVIDIA in Santa Clara, CA is seeking a Senior DFT Power Methodology Engineer to innovate DFT power, thermal and voltage-noise methodologies, enabling low-power manufacturing tests for datacenter GPUs.

You will collaborate with Product Development & Power Architecture, mentor junior engineers, apply AI/ML solutions to EDA challenges, and perform post-silicon data analysis to shape next‑gen products and test strategies.